xref: /openbmc/u-boot/include/configs/tuxx1.h (revision 3f82d89d)
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *                    Dave Liu <daveliu@freescale.com>
4  *
5  * Copyright (C) 2007 Logic Product Development, Inc.
6  *                    Peter Barada <peterb@logicpd.com>
7  *
8  * Copyright (C) 2007 MontaVista Software, Inc.
9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * (C) Copyright 2008
12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13  *
14  * (C) Copyright 2010-2012
15  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
16  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
17  *
18  * This program is free software; you can redistribute it and/or
19  * modify it under the terms of the GNU General Public License as
20  * published by the Free Software Foundation; either version 2 of
21  * the License, or (at your option) any later version.
22  */
23 
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26 
27 /*
28  * High Level Configuration Options
29  */
30 #ifdef CONFIG_KMSUPX5
31 #define CONFIG_KM_BOARD_NAME	"kmsupx5"
32 #define CONFIG_HOSTNAME		kmsupx5
33 #elif defined CONFIG_TUGE1
34 #define CONFIG_KM_BOARD_NAME	"tuge1"
35 #define CONFIG_HOSTNAME		tuge1
36 #else
37 #define CONFIG_TUXXX		/* TUXX1 board (tuxa1/tuda1) specific */
38 #define CONFIG_KM_BOARD_NAME	"tuxx1"
39 #define CONFIG_HOSTNAME		tuxx1
40 #endif
41 
42 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
43 
44 /* include common defines/options for all 8321 Keymile boards */
45 #include "km/km8321-common.h"
46 
47 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
48 #define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
49 #ifndef CONFIG_KM_DISABLE_APP2
50 #define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */
51 #define	CONFIG_SYS_APP2_SIZE	256 /* Megabytes */
52 #endif
53 
54 /*
55  * Init Local Bus Memory Controller:
56  *
57  * Bank Bus     Machine PortSz  Size  Device on TUDA1  TUXA1  TUGE1   KMSUPX4
58  * ---- ---     ------- ------  -----  ---------------------------------------
59  *  2   Local   GPCM    8 bit  256MB	         PAXG  LPXF   PAXI     LPXF
60  *  3   Local   GPCM    8 bit  256MB	         PINC3 PINC2  unused   unused
61  *
62  */
63 
64 /*
65  * Configuration for C2 on the local bus
66  */
67 /* Window base at flash base */
68 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
69 /* Window size: 256 MB */
70 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
71 
72 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
73 				 BR_PS_8 | \
74 				 BR_MS_GPCM | \
75 				 BR_V)
76 
77 #define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
78 				 OR_GPCM_CSNT | \
79 				 OR_GPCM_ACS_DIV4 | \
80 				 OR_GPCM_SCY_2 | \
81 				 OR_GPCM_TRLX_SET | \
82 				 OR_GPCM_EHTR_CLEAR | \
83 				 OR_GPCM_EAD)
84 #ifndef CONFIG_KM_DISABLE_APP2
85 /*
86  * Configuration for C3 on the local bus
87  */
88 /* Access window base at PINC3 base */
89 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
90 /* Window size: 256 MB */
91 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
92 
93 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
94 				 BR_PS_8 |		\
95 				 BR_MS_GPCM |		\
96 				 BR_V)
97 
98 #define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
99 				 OR_GPCM_CSNT |	\
100 				 OR_GPCM_ACS_DIV2 | \
101 				 OR_GPCM_SCY_2 | \
102 				 OR_GPCM_TRLX_SET | \
103 				 OR_GPCM_EHTR_CLEAR)
104 
105 #define CONFIG_SYS_MAMR		(MxMR_GPL_x4DIS | \
106 				 0x0000c000 | \
107 				 MxMR_WLFx_2X)
108 #endif
109 
110 /*
111  * MMU Setup
112  */
113 /* APP1: icache cacheable, but dcache-inhibit and guarded */
114 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | \
115 				 BATL_PP_RW | \
116 				 BATL_MEMCOHERENCE)
117 /* 512M should also include APP2... */
118 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | \
119 				 BATU_BL_256M | \
120 				 BATU_VS | \
121 				 BATU_VP)
122 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | \
123 				 BATL_PP_RW | \
124 				 BATL_CACHEINHIBIT | \
125 				 BATL_GUARDEDSTORAGE)
126 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
127 
128 #ifdef CONFIG_KM_DISABLE_APP2
129 #define CONFIG_SYS_IBAT6L	(0)
130 #define CONFIG_SYS_IBAT6U	(0)
131 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
132 #else
133 /* APP2:  icache cacheable, but dcache-inhibit and guarded */
134 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | \
135 				 BATL_PP_RW | \
136 				 BATL_MEMCOHERENCE)
137 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | \
138 				 BATU_BL_256M | \
139 				 BATU_VS | \
140 				 BATU_VP)
141 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | \
142 				 BATL_PP_RW | \
143 				 BATL_CACHEINHIBIT | \
144 				 BATL_GUARDEDSTORAGE)
145 #endif
146 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
147 
148 #define CONFIG_SYS_IBAT7L	(0)
149 #define CONFIG_SYS_IBAT7U	(0)
150 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
151 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
152 
153 #endif /* __CONFIG_H */
154