1 /* 2 * Copyright (C) 2015, Savoir-faire Linux Inc. 3 * 4 * Derived from MX51EVK code by 5 * Guennadi Liakhovetski <lg@denx.de> 6 * Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the TS4800 Board 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ 19 20 #define CONFIG_HW_WATCHDOG 21 22 #define CONFIG_MACH_TYPE MACH_TYPE_TS48XX 23 24 /* text base address used when linking */ 25 #define CONFIG_SYS_TEXT_BASE 0x90008000 26 27 #include <asm/arch/imx-regs.h> 28 29 /* enable passing of ATAGs */ 30 #define CONFIG_CMDLINE_TAG 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 39 40 /* 41 * Hardware drivers 42 */ 43 44 #define CONFIG_MXC_UART 45 #define CONFIG_MXC_UART_BASE UART1_BASE 46 #define CONFIG_MXC_GPIO 47 48 /* 49 * SPI Configs 50 * */ 51 #define CONFIG_HARD_SPI /* puts SPI: ready */ 52 #define CONFIG_MXC_SPI /* driver for the SPI controllers*/ 53 54 /* 55 * MMC Configs 56 * */ 57 #define CONFIG_FSL_ESDHC 58 #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR 59 60 /* 61 * Eth Configs 62 */ 63 #define CONFIG_MII 64 #define CONFIG_PHYLIB 65 #define CONFIG_PHY_SMSC 66 67 #define CONFIG_FEC_MXC 68 #define IMX_FEC_BASE FEC_BASE_ADDR 69 #define CONFIG_ETHPRIME "FEC" 70 #define CONFIG_FEC_MXC_PHYADDR 0 71 72 /* allow to overwrite serial and ethaddr */ 73 #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ 74 #define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ 75 76 /*********************************************************** 77 * Command definition 78 ***********************************************************/ 79 80 /* Environment variables */ 81 82 83 #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ 84 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 "script=boot.scr\0" \ 87 "image=zImage\0" \ 88 "fdt_file=imx51-ts4800.dtb\0" \ 89 "fdt_addr=0x90fe0000\0" \ 90 "mmcdev=0\0" \ 91 "mmcpart=2\0" \ 92 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ 93 "mmcargs=setenv bootargs root=${mmcroot}\0" \ 94 "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ 95 "loadbootscript=" \ 96 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 97 "bootscript=echo Running bootscript from mmc ...; " \ 98 "source\0" \ 99 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ 100 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 101 "mmcboot=echo Booting from mmc ...; " \ 102 "run mmcargs addtty; " \ 103 "if run loadfdt; then " \ 104 "bootz ${loadaddr} - ${fdt_addr}; " \ 105 "else " \ 106 "echo ERR: cannot load FDT; " \ 107 "fi; " 108 109 110 #define CONFIG_BOOTCOMMAND \ 111 "mmc dev ${mmcdev}; if mmc rescan; then " \ 112 "if run loadbootscript; then " \ 113 "run bootscript; " \ 114 "else " \ 115 "if run loadimage; then " \ 116 "run mmcboot; " \ 117 "fi; " \ 118 "fi; " \ 119 "fi; " 120 121 /* 122 * Miscellaneous configurable options 123 */ 124 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 125 #define CONFIG_AUTO_COMPLETE 126 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 127 /* Print Buffer Size */ 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 129 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 131 132 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 133 134 #define CONFIG_CMDLINE_EDITING 135 136 /*----------------------------------------------------------------------- 137 * Physical Memory Map 138 */ 139 #define CONFIG_NR_DRAM_BANKS 1 140 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 141 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) 142 143 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 144 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 145 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 146 147 #define CONFIG_SYS_INIT_SP_OFFSET \ 148 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 149 #define CONFIG_SYS_INIT_SP_ADDR \ 150 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 151 152 /* Low level init */ 153 #define CONFIG_SYS_DDR_CLKSEL 0 154 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 155 #define CONFIG_SYS_MAIN_PWR_ON 156 157 /*----------------------------------------------------------------------- 158 * Environment organization 159 */ 160 161 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 162 #define CONFIG_ENV_SIZE (8 * 1024) 163 #define CONFIG_SYS_MMC_ENV_DEV 0 164 165 #endif 166