xref: /openbmc/u-boot/include/configs/ts4800.h (revision ad3098f7)
1 /*
2  * Copyright (C) 2015, Savoir-faire Linux Inc.
3  *
4  * Derived from MX51EVK code by
5  *   Guennadi Liakhovetski <lg@denx.de>
6  *   Freescale Semiconductor, Inc.
7  *
8  * Configuration settings for the TS4800 Board
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 /* High Level Configuration Options */
17 #define CONFIG_MX51
18 
19 #define CONFIG_DISPLAY_CPUINFO
20 #define CONFIG_DISPLAY_BOARDINFO
21 
22 #define CONFIG_SYS_NO_FLASH		/* No NOR Flash */
23 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage bootloader */
24 
25 #define CONFIG_HW_WATCHDOG
26 
27 #define CONFIG_MACH_TYPE	MACH_TYPE_TS48XX
28 
29 /* text base address used when linking */
30 #define CONFIG_SYS_TEXT_BASE	0x90008000
31 
32 #include <asm/arch/imx-regs.h>
33 
34 /* enable passing of ATAGs */
35 #define CONFIG_CMDLINE_TAG
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_REVISION_TAG
39 
40 /*
41  * Size of malloc() pool
42  */
43 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
44 
45 /*
46  * Hardware drivers
47  */
48 
49 #define CONFIG_MXC_UART
50 #define CONFIG_MXC_UART_BASE	UART1_BASE
51 #define CONFIG_MXC_GPIO
52 
53 /*
54  * SPI Configs
55  * */
56 #define CONFIG_HARD_SPI /* puts SPI: ready */
57 #define CONFIG_MXC_SPI /* driver for the SPI controllers*/
58 
59 /*
60  * MMC Configs
61  * */
62 #define CONFIG_FSL_ESDHC
63 #define CONFIG_SYS_FSL_ESDHC_ADDR	MMC_SDHC1_BASE_ADDR
64 
65 #define CONFIG_MMC
66 
67 #define CONFIG_GENERIC_MMC
68 #define CONFIG_DOS_PARTITION
69 
70 /*
71  * Eth Configs
72  */
73 #define CONFIG_MII
74 #define CONFIG_PHYLIB
75 #define CONFIG_PHY_SMSC
76 
77 #define CONFIG_FEC_MXC
78 #define IMX_FEC_BASE	        FEC_BASE_ADDR
79 #define CONFIG_ETHPRIME		"FEC"
80 #define CONFIG_FEC_MXC_PHYADDR	0
81 
82 /* allow to overwrite serial and ethaddr */
83 #define CONFIG_ENV_OVERWRITE		/* disable vendor parameters protection (serial#, ethaddr) */
84 #define CONFIG_CONS_INDEX		1 /* use UART0 : used by serial driver */
85 #define CONFIG_BAUDRATE			115200
86 
87 /***********************************************************
88  * Command definition
89  ***********************************************************/
90 
91 /* Environment variables */
92 
93 #define CONFIG_BOOTDELAY	1
94 
95 #define CONFIG_LOADADDR		0x91000000	/* loadaddr env var */
96 
97 #define CONFIG_EXTRA_ENV_SETTINGS \
98 	"script=boot.scr\0" \
99 	"image=uImage\0" \
100 	"mmcdev=0\0" \
101 	"mmcpart=1\0" \
102 	"mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
103 	"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
104 	"loadbootscript=" \
105 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
106 	"bootscript=echo Running bootscript from mmc ...; " \
107 		"source\0" \
108 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
109 	"mmcboot=echo Booting from mmc ...; " \
110 		"run mmcargs addtty; " \
111                 "bootm; "
112 
113 #define CONFIG_BOOTCOMMAND \
114 	"mmc dev ${mmcdev}; if mmc rescan; then " \
115 		"if run loadbootscript; then " \
116 			"run bootscript; " \
117 		"else " \
118 			"if run loadimage; then " \
119 				"run mmcboot; " \
120 			"fi; " \
121 		"fi; " \
122 	"fi; "
123 
124 /*
125  * Miscellaneous configurable options
126  */
127 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
128 #define CONFIG_AUTO_COMPLETE
129 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
130 /* Print Buffer Size */
131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
132 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
134 
135 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
136 
137 #define CONFIG_CMDLINE_EDITING
138 
139 /*-----------------------------------------------------------------------
140  * Physical Memory Map
141  */
142 #define CONFIG_NR_DRAM_BANKS	1
143 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
144 #define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)
145 
146 #define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
147 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
148 #define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
149 
150 #define CONFIG_BOARD_EARLY_INIT_F
151 
152 #define CONFIG_SYS_INIT_SP_OFFSET \
153 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_ADDR \
155 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
156 
157 /* Low level init */
158 #define CONFIG_SYS_DDR_CLKSEL	0
159 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
160 #define CONFIG_SYS_MAIN_PWR_ON
161 
162 /*-----------------------------------------------------------------------
163  * Environment organization
164  */
165 
166 #define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
167 #define CONFIG_ENV_SIZE        (8 * 1024)
168 #define CONFIG_ENV_IS_IN_MMC
169 #define CONFIG_SYS_MMC_ENV_DEV 0
170 
171 #endif
172