1 /* 2 * Copyright (C) 2015, Savoir-faire Linux Inc. 3 * 4 * Derived from MX51EVK code by 5 * Guennadi Liakhovetski <lg@denx.de> 6 * Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the TS4800 Board 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ 19 20 #define CONFIG_HW_WATCHDOG 21 22 #define CONFIG_MACH_TYPE MACH_TYPE_TS48XX 23 24 /* text base address used when linking */ 25 #define CONFIG_SYS_TEXT_BASE 0x90008000 26 27 #include <asm/arch/imx-regs.h> 28 29 /* enable passing of ATAGs */ 30 #define CONFIG_CMDLINE_TAG 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 39 40 /* 41 * Hardware drivers 42 */ 43 44 #define CONFIG_MXC_UART 45 #define CONFIG_MXC_UART_BASE UART1_BASE 46 #define CONFIG_MXC_GPIO 47 48 /* 49 * SPI Configs 50 * */ 51 #define CONFIG_HARD_SPI /* puts SPI: ready */ 52 #define CONFIG_MXC_SPI /* driver for the SPI controllers*/ 53 54 /* 55 * MMC Configs 56 * */ 57 #define CONFIG_FSL_ESDHC 58 #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR 59 60 /* 61 * Eth Configs 62 */ 63 #define CONFIG_MII 64 #define CONFIG_PHY_SMSC 65 66 #define CONFIG_FEC_MXC 67 #define IMX_FEC_BASE FEC_BASE_ADDR 68 #define CONFIG_ETHPRIME "FEC" 69 #define CONFIG_FEC_MXC_PHYADDR 0 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ 73 #define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ 74 75 /*********************************************************** 76 * Command definition 77 ***********************************************************/ 78 79 /* Environment variables */ 80 81 82 #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ 83 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "script=boot.scr\0" \ 86 "image=zImage\0" \ 87 "fdt_file=imx51-ts4800.dtb\0" \ 88 "fdt_addr=0x90fe0000\0" \ 89 "mmcdev=0\0" \ 90 "mmcpart=2\0" \ 91 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ 92 "mmcargs=setenv bootargs root=${mmcroot}\0" \ 93 "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ 94 "loadbootscript=" \ 95 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 96 "bootscript=echo Running bootscript from mmc ...; " \ 97 "source\0" \ 98 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ 99 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 100 "mmcboot=echo Booting from mmc ...; " \ 101 "run mmcargs addtty; " \ 102 "if run loadfdt; then " \ 103 "bootz ${loadaddr} - ${fdt_addr}; " \ 104 "else " \ 105 "echo ERR: cannot load FDT; " \ 106 "fi; " 107 108 109 #define CONFIG_BOOTCOMMAND \ 110 "mmc dev ${mmcdev}; if mmc rescan; then " \ 111 "if run loadbootscript; then " \ 112 "run bootscript; " \ 113 "else " \ 114 "if run loadimage; then " \ 115 "run mmcboot; " \ 116 "fi; " \ 117 "fi; " \ 118 "fi; " 119 120 /* 121 * Miscellaneous configurable options 122 */ 123 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 124 #define CONFIG_AUTO_COMPLETE 125 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 126 /* Print Buffer Size */ 127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 128 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 129 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 130 131 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 132 133 #define CONFIG_CMDLINE_EDITING 134 135 /*----------------------------------------------------------------------- 136 * Physical Memory Map 137 */ 138 #define CONFIG_NR_DRAM_BANKS 1 139 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 140 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) 141 142 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 143 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 144 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 145 146 #define CONFIG_SYS_INIT_SP_OFFSET \ 147 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 148 #define CONFIG_SYS_INIT_SP_ADDR \ 149 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 150 151 /* Low level init */ 152 #define CONFIG_SYS_DDR_CLKSEL 0 153 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 154 #define CONFIG_SYS_MAIN_PWR_ON 155 156 /*----------------------------------------------------------------------- 157 * Environment organization 158 */ 159 160 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 161 #define CONFIG_ENV_SIZE (8 * 1024) 162 #define CONFIG_SYS_MMC_ENV_DEV 0 163 164 #endif 165