1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 20 /* 21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 22 * 64 bytes before this address should be set aside for u-boot.img's 23 * header. That is 0x800FFFC0--0x80100000 should not be used for any 24 * other needs. 25 */ 26 #define CONFIG_SYS_TEXT_BASE 0x80100000 27 28 #define CONFIG_SDRC /* The chip has SDRC controller */ 29 30 #include <asm/arch/cpu.h> /* get chip and board defs */ 31 #include <asm/arch/omap.h> 32 33 /* Clock Defines */ 34 #define V_OSCK 26000000 /* Clock output from T2 */ 35 #define V_SCLK (V_OSCK >> 1) 36 37 #define CONFIG_MISC_INIT_R 38 39 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 40 #define CONFIG_SETUP_MEMORY_TAGS 41 #define CONFIG_INITRD_TAG 42 #define CONFIG_REVISION_TAG 43 44 /* Size of malloc() pool */ 45 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 46 47 /* Hardware drivers */ 48 49 /* NS16550 Configuration */ 50 #define CONFIG_SYS_NS16550_SERIAL 51 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 52 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 53 54 /* select serial console configuration */ 55 #define CONFIG_CONS_INDEX 3 56 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 57 #define CONFIG_SERIAL3 3 58 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 59 115200} 60 61 /* I2C */ 62 #define CONFIG_SYS_I2C 63 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 64 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 65 66 67 /* EEPROM */ 68 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 69 #define CONFIG_SYS_EEPROM_BUS_NUM 1 70 71 /* TWL4030 */ 72 #define CONFIG_TWL4030_LED 73 74 /* Board NAND Info */ 75 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 76 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 77 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 78 "128k(SPL)," \ 79 "1m(u-boot)," \ 80 "384k(u-boot-env1)," \ 81 "1152k(mtdoops)," \ 82 "384k(u-boot-env2)," \ 83 "5m(kernel)," \ 84 "2m(fdt)," \ 85 "-(ubi)" 86 87 #define CONFIG_NAND_OMAP_GPMC 88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 89 /* to access nand */ 90 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 91 /* to access nand at */ 92 /* CS0 */ 93 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 94 /* devices */ 95 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 96 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 97 98 /* needed for ubi */ 99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 100 #define CONFIG_MTD_PARTITIONS 101 102 /* Environment information (this is the common part) */ 103 104 105 /* hang() the board on panic() */ 106 #define CONFIG_PANIC_HANG 107 108 /* environment placement (for NAND), is different for FLASHCARD but does not 109 * harm there */ 110 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 111 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 112 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 113 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 114 115 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 116 * value can not be used here! */ 117 #define CONFIG_LOADADDR 0x82000000 118 119 #define CONFIG_COMMON_ENV_SETTINGS \ 120 "console=ttyO2,115200n8\0" \ 121 "mmcdev=0\0" \ 122 "vram=3M\0" \ 123 "defaultdisplay=lcd\0" \ 124 "kernelopts=mtdoops.mtddev=3\0" \ 125 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 126 "mtdids=" MTDIDS_DEFAULT "\0" \ 127 "commonargs=" \ 128 "setenv bootargs console=${console} " \ 129 "${mtdparts} " \ 130 "${kernelopts} " \ 131 "vt.global_cursor_default=0 " \ 132 "vram=${vram} " \ 133 "omapdss.def_disp=${defaultdisplay}\0" 134 135 #define CONFIG_BOOTCOMMAND "run autoboot" 136 137 /* specific environment settings for different use cases 138 * FLASHCARD: used to run a rdimage from sdcard to program the device 139 * 'NORMAL': used to boot kernel from sdcard, nand, ... 140 * 141 * The main aim for the FLASHCARD skin is to have an embedded environment 142 * which will not be influenced by any data already on the device. 143 */ 144 #ifdef CONFIG_FLASHCARD 145 /* the rdaddr is 16 MiB before the loadaddr */ 146 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 147 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 CONFIG_COMMON_ENV_SETTINGS \ 150 CONFIG_ENV_RDADDR \ 151 "autoboot=" \ 152 "run commonargs; " \ 153 "setenv bootargs ${bootargs} " \ 154 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 155 "rdinit=/sbin/init; " \ 156 "mmc dev ${mmcdev}; mmc rescan; " \ 157 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 158 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 159 "bootm ${loadaddr} ${rdaddr}\0" 160 161 #else /* CONFIG_FLASHCARD */ 162 163 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 164 165 #define CONFIG_EXTRA_ENV_SETTINGS \ 166 CONFIG_COMMON_ENV_SETTINGS \ 167 "mmcargs=" \ 168 "run commonargs; " \ 169 "setenv bootargs ${bootargs} " \ 170 "root=/dev/mmcblk0p2 " \ 171 "rootwait " \ 172 "rw\0" \ 173 "nandargs=" \ 174 "run commonargs; " \ 175 "setenv bootargs ${bootargs} " \ 176 "root=ubi0:root " \ 177 "ubi.mtd=7 " \ 178 "rootfstype=ubifs " \ 179 "ro\0" \ 180 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 181 "bootscript=echo Running bootscript from mmc ...; " \ 182 "source ${loadaddr}\0" \ 183 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 184 "mmcboot=echo Booting from mmc ...; " \ 185 "run mmcargs; " \ 186 "bootm ${loadaddr}\0" \ 187 "loaduimage_ubi=ubi part ubi; " \ 188 "ubifsmount ubi:root; " \ 189 "ubifsload ${loadaddr} /boot/uImage\0" \ 190 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 191 "nandboot=echo Booting from nand ...; " \ 192 "run nandargs; " \ 193 "run loaduimage_nand; " \ 194 "bootm ${loadaddr}\0" \ 195 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 196 "if run loadbootscript; then " \ 197 "run bootscript; " \ 198 "else " \ 199 "if run loaduimage; then " \ 200 "run mmcboot; " \ 201 "else run nandboot; " \ 202 "fi; " \ 203 "fi; " \ 204 "else run nandboot; fi\0" 205 206 #endif /* CONFIG_FLASHCARD */ 207 208 /* Miscellaneous configurable options */ 209 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 210 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 211 #define CONFIG_AUTO_COMPLETE 212 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 213 214 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 215 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 216 0x07000000) /* 112 MB */ 217 218 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 219 220 /* 221 * OMAP3 has 12 GP timers, they can be driven by the system clock 222 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 223 * This rate is divided by a local divisor. 224 */ 225 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 226 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 227 228 /* Physical Memory Map */ 229 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 230 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 231 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 232 233 /* NAND and environment organization */ 234 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 235 236 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 237 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 238 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 239 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 240 CONFIG_SYS_INIT_RAM_SIZE - \ 241 GENERATED_GBL_DATA_SIZE) 242 243 /* SRAM config */ 244 #define CONFIG_SYS_SRAM_START 0x40200000 245 #define CONFIG_SYS_SRAM_SIZE 0x10000 246 247 /* Defines for SPL */ 248 #define CONFIG_SPL_FRAMEWORK 249 #define CONFIG_SPL_NAND_SIMPLE 250 251 #define CONFIG_SPL_NAND_BASE 252 #define CONFIG_SPL_NAND_DRIVERS 253 #define CONFIG_SPL_NAND_ECC 254 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 255 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 256 257 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 258 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 259 CONFIG_SPL_TEXT_BASE) 260 261 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 262 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 263 264 /* NAND boot config */ 265 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 266 #define CONFIG_SYS_NAND_PAGE_COUNT 64 267 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 268 #define CONFIG_SYS_NAND_OOBSIZE 64 269 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 270 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 271 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 272 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 273 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 274 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 275 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 276 52, 53, 54, 55, 56} 277 278 #define CONFIG_SYS_NAND_ECCSIZE 512 279 #define CONFIG_SYS_NAND_ECCBYTES 13 280 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 281 282 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 283 284 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 285 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 286 287 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 288 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 289 290 #define CONFIG_SYS_ALT_MEMTEST 291 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 292 #endif /* __CONFIG_H */ 293