1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_THUMB_BUILD 21 #define CONFIG_OMAP /* in a TI OMAP core */ 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 28 /* 29 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 30 * 64 bytes before this address should be set aside for u-boot.img's 31 * header. That is 0x800FFFC0--0x80100000 should not be used for any 32 * other needs. 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0x80100000 35 36 #define CONFIG_SDRC /* The chip has SDRC controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap.h> 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 48 #define CONFIG_SETUP_MEMORY_TAGS 49 #define CONFIG_INITRD_TAG 50 #define CONFIG_REVISION_TAG 51 52 /* Size of malloc() pool */ 53 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 54 55 /* Hardware drivers */ 56 57 /* GPIO support */ 58 #define CONFIG_OMAP_GPIO 59 60 /* GPIO banks */ 61 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 62 63 /* LED support */ 64 65 /* NS16550 Configuration */ 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 /* select serial console configuration */ 71 #define CONFIG_CONS_INDEX 3 72 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 73 #define CONFIG_SERIAL3 3 74 #define CONFIG_BAUDRATE 115200 75 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 76 115200} 77 78 /* I2C */ 79 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 81 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 82 #define CONFIG_SYS_I2C_OMAP34XX 83 84 85 /* EEPROM */ 86 #define CONFIG_CMD_EEPROM 87 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 88 #define CONFIG_SYS_EEPROM_BUS_NUM 1 89 90 /* TWL4030 */ 91 #define CONFIG_TWL4030_POWER 92 #define CONFIG_TWL4030_LED 93 94 /* Board NAND Info */ 95 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 96 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 97 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 98 "128k(SPL)," \ 99 "1m(u-boot)," \ 100 "384k(u-boot-env1)," \ 101 "1152k(mtdoops)," \ 102 "384k(u-boot-env2)," \ 103 "5m(kernel)," \ 104 "2m(fdt)," \ 105 "-(ubi)" 106 107 #define CONFIG_NAND_OMAP_GPMC 108 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 109 /* to access nand */ 110 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 111 /* to access nand at */ 112 /* CS0 */ 113 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 114 /* devices */ 115 #define CONFIG_BCH 116 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 117 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 118 119 /* commands to include */ 120 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 121 #define CONFIG_CMD_NAND /* NAND support */ 122 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 123 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 124 #define CONFIG_LZO /* LZO is needed for UBIFS */ 125 126 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 127 128 /* needed for ubi */ 129 #define CONFIG_RBTREE 130 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 131 #define CONFIG_MTD_PARTITIONS 132 133 /* Environment information (this is the common part) */ 134 135 136 /* hang() the board on panic() */ 137 #define CONFIG_PANIC_HANG 138 139 /* environment placement (for NAND), is different for FLASHCARD but does not 140 * harm there */ 141 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 142 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 143 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 144 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 145 146 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 147 * value can not be used here! */ 148 #define CONFIG_LOADADDR 0x82000000 149 150 #define CONFIG_COMMON_ENV_SETTINGS \ 151 "console=ttyO2,115200n8\0" \ 152 "mmcdev=0\0" \ 153 "vram=3M\0" \ 154 "defaultdisplay=lcd\0" \ 155 "kernelopts=mtdoops.mtddev=3\0" \ 156 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 157 "mtdids=" MTDIDS_DEFAULT "\0" \ 158 "commonargs=" \ 159 "setenv bootargs console=${console} " \ 160 "${mtdparts} " \ 161 "${kernelopts} " \ 162 "vt.global_cursor_default=0 " \ 163 "vram=${vram} " \ 164 "omapdss.def_disp=${defaultdisplay}\0" 165 166 #define CONFIG_BOOTCOMMAND "run autoboot" 167 168 /* specific environment settings for different use cases 169 * FLASHCARD: used to run a rdimage from sdcard to program the device 170 * 'NORMAL': used to boot kernel from sdcard, nand, ... 171 * 172 * The main aim for the FLASHCARD skin is to have an embedded environment 173 * which will not be influenced by any data already on the device. 174 */ 175 #ifdef CONFIG_FLASHCARD 176 177 #define CONFIG_ENV_IS_NOWHERE 178 179 /* the rdaddr is 16 MiB before the loadaddr */ 180 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 181 182 #define CONFIG_EXTRA_ENV_SETTINGS \ 183 CONFIG_COMMON_ENV_SETTINGS \ 184 CONFIG_ENV_RDADDR \ 185 "autoboot=" \ 186 "run commonargs; " \ 187 "setenv bootargs ${bootargs} " \ 188 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 189 "rdinit=/sbin/init; " \ 190 "mmc dev ${mmcdev}; mmc rescan; " \ 191 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 192 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 193 "bootm ${loadaddr} ${rdaddr}\0" 194 195 #else /* CONFIG_FLASHCARD */ 196 197 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 198 199 #define CONFIG_ENV_IS_IN_NAND 200 201 #define CONFIG_EXTRA_ENV_SETTINGS \ 202 CONFIG_COMMON_ENV_SETTINGS \ 203 "mmcargs=" \ 204 "run commonargs; " \ 205 "setenv bootargs ${bootargs} " \ 206 "root=/dev/mmcblk0p2 " \ 207 "rootwait " \ 208 "rw\0" \ 209 "nandargs=" \ 210 "run commonargs; " \ 211 "setenv bootargs ${bootargs} " \ 212 "root=ubi0:root " \ 213 "ubi.mtd=7 " \ 214 "rootfstype=ubifs " \ 215 "ro\0" \ 216 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 217 "bootscript=echo Running bootscript from mmc ...; " \ 218 "source ${loadaddr}\0" \ 219 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 220 "mmcboot=echo Booting from mmc ...; " \ 221 "run mmcargs; " \ 222 "bootm ${loadaddr}\0" \ 223 "loaduimage_ubi=ubi part ubi; " \ 224 "ubifsmount ubi:root; " \ 225 "ubifsload ${loadaddr} /boot/uImage\0" \ 226 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 227 "nandboot=echo Booting from nand ...; " \ 228 "run nandargs; " \ 229 "run loaduimage_nand; " \ 230 "bootm ${loadaddr}\0" \ 231 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 232 "if run loadbootscript; then " \ 233 "run bootscript; " \ 234 "else " \ 235 "if run loaduimage; then " \ 236 "run mmcboot; " \ 237 "else run nandboot; " \ 238 "fi; " \ 239 "fi; " \ 240 "else run nandboot; fi\0" 241 242 #endif /* CONFIG_FLASHCARD */ 243 244 /* Miscellaneous configurable options */ 245 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 246 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 247 #define CONFIG_AUTO_COMPLETE 248 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 249 /* Print Buffer Size */ 250 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 251 sizeof(CONFIG_SYS_PROMPT) + 16) 252 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 253 254 /* Boot Argument Buffer Size */ 255 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 256 257 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 258 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 259 0x07000000) /* 112 MB */ 260 261 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 262 263 /* 264 * OMAP3 has 12 GP timers, they can be driven by the system clock 265 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 266 * This rate is divided by a local divisor. 267 */ 268 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 269 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 270 271 /* Physical Memory Map */ 272 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 273 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 274 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 275 276 /* NAND and environment organization */ 277 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 278 279 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 280 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 281 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 282 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 283 CONFIG_SYS_INIT_RAM_SIZE - \ 284 GENERATED_GBL_DATA_SIZE) 285 286 /* SRAM config */ 287 #define CONFIG_SYS_SRAM_START 0x40200000 288 #define CONFIG_SYS_SRAM_SIZE 0x10000 289 290 /* Defines for SPL */ 291 #define CONFIG_SPL_FRAMEWORK 292 #define CONFIG_SPL_NAND_SIMPLE 293 294 #define CONFIG_SPL_BOARD_INIT 295 #define CONFIG_SPL_NAND_BASE 296 #define CONFIG_SPL_NAND_DRIVERS 297 #define CONFIG_SPL_NAND_ECC 298 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 299 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 300 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 301 302 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 303 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 304 CONFIG_SPL_TEXT_BASE) 305 306 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 307 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 308 309 /* NAND boot config */ 310 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 311 #define CONFIG_SYS_NAND_PAGE_COUNT 64 312 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 313 #define CONFIG_SYS_NAND_OOBSIZE 64 314 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 315 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 316 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 317 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 318 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 319 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 320 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 321 52, 53, 54, 55, 56} 322 323 #define CONFIG_SYS_NAND_ECCSIZE 512 324 #define CONFIG_SYS_NAND_ECCBYTES 13 325 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 326 327 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 328 329 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 330 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 331 332 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 333 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 334 335 #define CONFIG_SYS_ALT_MEMTEST 336 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 337 #endif /* __CONFIG_H */ 338