1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_THUMB_BUILD 21 #define CONFIG_OMAP /* in a TI OMAP core */ 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 28 /* 29 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 30 * 64 bytes before this address should be set aside for u-boot.img's 31 * header. That is 0x800FFFC0--0x80100000 should not be used for any 32 * other needs. 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0x80100000 35 36 #define CONFIG_SDRC /* The chip has SDRC controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap.h> 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 48 #define CONFIG_SETUP_MEMORY_TAGS 49 #define CONFIG_INITRD_TAG 50 #define CONFIG_REVISION_TAG 51 52 /* Size of malloc() pool */ 53 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 54 55 /* Hardware drivers */ 56 57 /* GPIO support */ 58 #define CONFIG_OMAP_GPIO 59 60 /* GPIO banks */ 61 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 62 63 /* LED support */ 64 65 /* NS16550 Configuration */ 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 /* select serial console configuration */ 71 #define CONFIG_CONS_INDEX 3 72 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 73 #define CONFIG_SERIAL3 3 74 #define CONFIG_BAUDRATE 115200 75 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 76 115200} 77 78 /* MMC */ 79 #define CONFIG_GENERIC_MMC 80 81 /* I2C */ 82 #define CONFIG_SYS_I2C 83 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 84 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 85 #define CONFIG_SYS_I2C_OMAP34XX 86 87 88 /* EEPROM */ 89 #define CONFIG_CMD_EEPROM 90 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 91 #define CONFIG_SYS_EEPROM_BUS_NUM 1 92 93 /* TWL4030 */ 94 #define CONFIG_TWL4030_POWER 95 #define CONFIG_TWL4030_LED 96 97 /* Board NAND Info */ 98 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 100 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 101 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 102 "128k(SPL)," \ 103 "1m(u-boot)," \ 104 "384k(u-boot-env1)," \ 105 "1152k(mtdoops)," \ 106 "384k(u-boot-env2)," \ 107 "5m(kernel)," \ 108 "2m(fdt)," \ 109 "-(ubi)" 110 111 #define CONFIG_NAND_OMAP_GPMC 112 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 113 /* to access nand */ 114 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 115 /* to access nand at */ 116 /* CS0 */ 117 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 118 /* devices */ 119 #define CONFIG_BCH 120 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 121 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 122 123 /* commands to include */ 124 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 125 #define CONFIG_CMD_NAND /* NAND support */ 126 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 127 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 128 #define CONFIG_LZO /* LZO is needed for UBIFS */ 129 130 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 131 132 /* needed for ubi */ 133 #define CONFIG_RBTREE 134 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 135 #define CONFIG_MTD_PARTITIONS 136 137 /* Environment information (this is the common part) */ 138 139 140 /* hang() the board on panic() */ 141 #define CONFIG_PANIC_HANG 142 143 /* environment placement (for NAND), is different for FLASHCARD but does not 144 * harm there */ 145 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 146 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 147 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 148 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 149 150 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 151 * value can not be used here! */ 152 #define CONFIG_LOADADDR 0x82000000 153 154 #define CONFIG_COMMON_ENV_SETTINGS \ 155 "console=ttyO2,115200n8\0" \ 156 "mmcdev=0\0" \ 157 "vram=3M\0" \ 158 "defaultdisplay=lcd\0" \ 159 "kernelopts=mtdoops.mtddev=3\0" \ 160 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 161 "mtdids=" MTDIDS_DEFAULT "\0" \ 162 "commonargs=" \ 163 "setenv bootargs console=${console} " \ 164 "${mtdparts} " \ 165 "${kernelopts} " \ 166 "vt.global_cursor_default=0 " \ 167 "vram=${vram} " \ 168 "omapdss.def_disp=${defaultdisplay}\0" 169 170 #define CONFIG_BOOTCOMMAND "run autoboot" 171 172 /* specific environment settings for different use cases 173 * FLASHCARD: used to run a rdimage from sdcard to program the device 174 * 'NORMAL': used to boot kernel from sdcard, nand, ... 175 * 176 * The main aim for the FLASHCARD skin is to have an embedded environment 177 * which will not be influenced by any data already on the device. 178 */ 179 #ifdef CONFIG_FLASHCARD 180 181 #define CONFIG_ENV_IS_NOWHERE 182 183 /* the rdaddr is 16 MiB before the loadaddr */ 184 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 185 186 #define CONFIG_EXTRA_ENV_SETTINGS \ 187 CONFIG_COMMON_ENV_SETTINGS \ 188 CONFIG_ENV_RDADDR \ 189 "autoboot=" \ 190 "run commonargs; " \ 191 "setenv bootargs ${bootargs} " \ 192 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 193 "rdinit=/sbin/init; " \ 194 "mmc dev ${mmcdev}; mmc rescan; " \ 195 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 196 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 197 "bootm ${loadaddr} ${rdaddr}\0" 198 199 #else /* CONFIG_FLASHCARD */ 200 201 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 202 203 #define CONFIG_ENV_IS_IN_NAND 204 205 #define CONFIG_EXTRA_ENV_SETTINGS \ 206 CONFIG_COMMON_ENV_SETTINGS \ 207 "mmcargs=" \ 208 "run commonargs; " \ 209 "setenv bootargs ${bootargs} " \ 210 "root=/dev/mmcblk0p2 " \ 211 "rootwait " \ 212 "rw\0" \ 213 "nandargs=" \ 214 "run commonargs; " \ 215 "setenv bootargs ${bootargs} " \ 216 "root=ubi0:root " \ 217 "ubi.mtd=7 " \ 218 "rootfstype=ubifs " \ 219 "ro\0" \ 220 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 221 "bootscript=echo Running bootscript from mmc ...; " \ 222 "source ${loadaddr}\0" \ 223 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 224 "mmcboot=echo Booting from mmc ...; " \ 225 "run mmcargs; " \ 226 "bootm ${loadaddr}\0" \ 227 "loaduimage_ubi=ubi part ubi; " \ 228 "ubifsmount ubi:root; " \ 229 "ubifsload ${loadaddr} /boot/uImage\0" \ 230 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 231 "nandboot=echo Booting from nand ...; " \ 232 "run nandargs; " \ 233 "run loaduimage_nand; " \ 234 "bootm ${loadaddr}\0" \ 235 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 236 "if run loadbootscript; then " \ 237 "run bootscript; " \ 238 "else " \ 239 "if run loaduimage; then " \ 240 "run mmcboot; " \ 241 "else run nandboot; " \ 242 "fi; " \ 243 "fi; " \ 244 "else run nandboot; fi\0" 245 246 #endif /* CONFIG_FLASHCARD */ 247 248 /* Miscellaneous configurable options */ 249 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 250 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 251 #define CONFIG_AUTO_COMPLETE 252 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 253 /* Print Buffer Size */ 254 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 255 sizeof(CONFIG_SYS_PROMPT) + 16) 256 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 257 258 /* Boot Argument Buffer Size */ 259 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 260 261 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 262 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 263 0x07000000) /* 112 MB */ 264 265 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 266 267 /* 268 * OMAP3 has 12 GP timers, they can be driven by the system clock 269 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 270 * This rate is divided by a local divisor. 271 */ 272 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 273 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 274 275 /* Physical Memory Map */ 276 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 277 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 278 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 279 280 /* NAND and environment organization */ 281 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 282 283 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 284 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 285 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 286 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 287 CONFIG_SYS_INIT_RAM_SIZE - \ 288 GENERATED_GBL_DATA_SIZE) 289 290 /* SRAM config */ 291 #define CONFIG_SYS_SRAM_START 0x40200000 292 #define CONFIG_SYS_SRAM_SIZE 0x10000 293 294 /* Defines for SPL */ 295 #define CONFIG_SPL_FRAMEWORK 296 #define CONFIG_SPL_NAND_SIMPLE 297 298 #define CONFIG_SPL_BOARD_INIT 299 #define CONFIG_SPL_NAND_BASE 300 #define CONFIG_SPL_NAND_DRIVERS 301 #define CONFIG_SPL_NAND_ECC 302 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 303 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 304 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 305 306 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 307 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 308 CONFIG_SPL_TEXT_BASE) 309 310 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 311 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 312 313 /* NAND boot config */ 314 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 315 #define CONFIG_SYS_NAND_PAGE_COUNT 64 316 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 317 #define CONFIG_SYS_NAND_OOBSIZE 64 318 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 319 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 320 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 321 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 322 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 323 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 324 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 325 52, 53, 54, 55, 56} 326 327 #define CONFIG_SYS_NAND_ECCSIZE 512 328 #define CONFIG_SYS_NAND_ECCBYTES 13 329 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 330 331 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 332 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 334 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 335 336 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 337 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 338 339 #define CONFIG_SYS_ALT_MEMTEST 340 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 341 #endif /* __CONFIG_H */ 342