1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_OMAP /* in a TI OMAP core */ 21 22 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 23 /* 24 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 25 * 64 bytes before this address should be set aside for u-boot.img's 26 * header. That is 0x800FFFC0--0x80100000 should not be used for any 27 * other needs. 28 */ 29 #define CONFIG_SYS_TEXT_BASE 0x80100000 30 31 #define CONFIG_SDRC /* The chip has SDRC controller */ 32 33 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/omap.h> 35 36 /* Clock Defines */ 37 #define V_OSCK 26000000 /* Clock output from T2 */ 38 #define V_SCLK (V_OSCK >> 1) 39 40 #define CONFIG_MISC_INIT_R 41 42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43 #define CONFIG_SETUP_MEMORY_TAGS 44 #define CONFIG_INITRD_TAG 45 #define CONFIG_REVISION_TAG 46 47 /* Size of malloc() pool */ 48 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 49 50 /* Hardware drivers */ 51 52 /* GPIO support */ 53 #define CONFIG_OMAP_GPIO 54 55 /* GPIO banks */ 56 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 57 58 /* LED support */ 59 60 /* NS16550 Configuration */ 61 #define CONFIG_SYS_NS16550_SERIAL 62 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 63 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 64 65 /* select serial console configuration */ 66 #define CONFIG_CONS_INDEX 3 67 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 68 #define CONFIG_SERIAL3 3 69 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 70 115200} 71 72 /* I2C */ 73 #define CONFIG_SYS_I2C 74 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 75 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 76 #define CONFIG_SYS_I2C_OMAP34XX 77 78 79 /* EEPROM */ 80 #define CONFIG_CMD_EEPROM 81 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 82 #define CONFIG_SYS_EEPROM_BUS_NUM 1 83 84 /* TWL4030 */ 85 #define CONFIG_TWL4030_LED 86 87 /* Board NAND Info */ 88 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 89 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 90 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 91 "128k(SPL)," \ 92 "1m(u-boot)," \ 93 "384k(u-boot-env1)," \ 94 "1152k(mtdoops)," \ 95 "384k(u-boot-env2)," \ 96 "5m(kernel)," \ 97 "2m(fdt)," \ 98 "-(ubi)" 99 100 #define CONFIG_NAND_OMAP_GPMC 101 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 102 /* to access nand */ 103 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 104 /* to access nand at */ 105 /* CS0 */ 106 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 107 /* devices */ 108 #define CONFIG_BCH 109 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 110 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 111 112 /* commands to include */ 113 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 114 #define CONFIG_CMD_NAND /* NAND support */ 115 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 116 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 117 #define CONFIG_LZO /* LZO is needed for UBIFS */ 118 119 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 120 121 /* needed for ubi */ 122 #define CONFIG_RBTREE 123 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 124 #define CONFIG_MTD_PARTITIONS 125 126 /* Environment information (this is the common part) */ 127 128 129 /* hang() the board on panic() */ 130 #define CONFIG_PANIC_HANG 131 132 /* environment placement (for NAND), is different for FLASHCARD but does not 133 * harm there */ 134 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 135 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 136 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 137 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 138 139 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 140 * value can not be used here! */ 141 #define CONFIG_LOADADDR 0x82000000 142 143 #define CONFIG_COMMON_ENV_SETTINGS \ 144 "console=ttyO2,115200n8\0" \ 145 "mmcdev=0\0" \ 146 "vram=3M\0" \ 147 "defaultdisplay=lcd\0" \ 148 "kernelopts=mtdoops.mtddev=3\0" \ 149 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 150 "mtdids=" MTDIDS_DEFAULT "\0" \ 151 "commonargs=" \ 152 "setenv bootargs console=${console} " \ 153 "${mtdparts} " \ 154 "${kernelopts} " \ 155 "vt.global_cursor_default=0 " \ 156 "vram=${vram} " \ 157 "omapdss.def_disp=${defaultdisplay}\0" 158 159 #define CONFIG_BOOTCOMMAND "run autoboot" 160 161 /* specific environment settings for different use cases 162 * FLASHCARD: used to run a rdimage from sdcard to program the device 163 * 'NORMAL': used to boot kernel from sdcard, nand, ... 164 * 165 * The main aim for the FLASHCARD skin is to have an embedded environment 166 * which will not be influenced by any data already on the device. 167 */ 168 #ifdef CONFIG_FLASHCARD 169 170 #define CONFIG_ENV_IS_NOWHERE 171 172 /* the rdaddr is 16 MiB before the loadaddr */ 173 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 174 175 #define CONFIG_EXTRA_ENV_SETTINGS \ 176 CONFIG_COMMON_ENV_SETTINGS \ 177 CONFIG_ENV_RDADDR \ 178 "autoboot=" \ 179 "run commonargs; " \ 180 "setenv bootargs ${bootargs} " \ 181 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 182 "rdinit=/sbin/init; " \ 183 "mmc dev ${mmcdev}; mmc rescan; " \ 184 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 185 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 186 "bootm ${loadaddr} ${rdaddr}\0" 187 188 #else /* CONFIG_FLASHCARD */ 189 190 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 191 192 #define CONFIG_ENV_IS_IN_NAND 193 194 #define CONFIG_EXTRA_ENV_SETTINGS \ 195 CONFIG_COMMON_ENV_SETTINGS \ 196 "mmcargs=" \ 197 "run commonargs; " \ 198 "setenv bootargs ${bootargs} " \ 199 "root=/dev/mmcblk0p2 " \ 200 "rootwait " \ 201 "rw\0" \ 202 "nandargs=" \ 203 "run commonargs; " \ 204 "setenv bootargs ${bootargs} " \ 205 "root=ubi0:root " \ 206 "ubi.mtd=7 " \ 207 "rootfstype=ubifs " \ 208 "ro\0" \ 209 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 210 "bootscript=echo Running bootscript from mmc ...; " \ 211 "source ${loadaddr}\0" \ 212 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 213 "mmcboot=echo Booting from mmc ...; " \ 214 "run mmcargs; " \ 215 "bootm ${loadaddr}\0" \ 216 "loaduimage_ubi=ubi part ubi; " \ 217 "ubifsmount ubi:root; " \ 218 "ubifsload ${loadaddr} /boot/uImage\0" \ 219 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 220 "nandboot=echo Booting from nand ...; " \ 221 "run nandargs; " \ 222 "run loaduimage_nand; " \ 223 "bootm ${loadaddr}\0" \ 224 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 225 "if run loadbootscript; then " \ 226 "run bootscript; " \ 227 "else " \ 228 "if run loaduimage; then " \ 229 "run mmcboot; " \ 230 "else run nandboot; " \ 231 "fi; " \ 232 "fi; " \ 233 "else run nandboot; fi\0" 234 235 #endif /* CONFIG_FLASHCARD */ 236 237 /* Miscellaneous configurable options */ 238 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 239 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 240 #define CONFIG_AUTO_COMPLETE 241 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 242 /* Print Buffer Size */ 243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 244 sizeof(CONFIG_SYS_PROMPT) + 16) 245 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 246 247 /* Boot Argument Buffer Size */ 248 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 249 250 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 251 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 252 0x07000000) /* 112 MB */ 253 254 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 255 256 /* 257 * OMAP3 has 12 GP timers, they can be driven by the system clock 258 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 259 * This rate is divided by a local divisor. 260 */ 261 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 262 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 263 264 /* Physical Memory Map */ 265 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 266 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 267 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 268 269 /* NAND and environment organization */ 270 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 271 272 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 273 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 274 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 275 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 276 CONFIG_SYS_INIT_RAM_SIZE - \ 277 GENERATED_GBL_DATA_SIZE) 278 279 /* SRAM config */ 280 #define CONFIG_SYS_SRAM_START 0x40200000 281 #define CONFIG_SYS_SRAM_SIZE 0x10000 282 283 /* Defines for SPL */ 284 #define CONFIG_SPL_FRAMEWORK 285 #define CONFIG_SPL_NAND_SIMPLE 286 287 #define CONFIG_SPL_BOARD_INIT 288 #define CONFIG_SPL_NAND_BASE 289 #define CONFIG_SPL_NAND_DRIVERS 290 #define CONFIG_SPL_NAND_ECC 291 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 292 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 293 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 294 295 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 296 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 297 CONFIG_SPL_TEXT_BASE) 298 299 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 300 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 301 302 /* NAND boot config */ 303 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 304 #define CONFIG_SYS_NAND_PAGE_COUNT 64 305 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 306 #define CONFIG_SYS_NAND_OOBSIZE 64 307 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 308 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 309 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 310 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 311 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 312 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 313 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 314 52, 53, 54, 55, 56} 315 316 #define CONFIG_SYS_NAND_ECCSIZE 512 317 #define CONFIG_SYS_NAND_ECCBYTES 13 318 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 319 320 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 321 322 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 323 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 324 325 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 326 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 327 328 #define CONFIG_SYS_ALT_MEMTEST 329 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 330 #endif /* __CONFIG_H */ 331