1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_OMAP /* in a TI OMAP core */ 21 #define CONFIG_OMAP34XX /* which is a 34XX */ 22 #define CONFIG_OMAP_COMMON 23 24 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 25 /* 26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 27 * 64 bytes before this address should be set aside for u-boot.img's 28 * header. That is 0x800FFFC0--0x80100000 should not be used for any 29 * other needs. 30 */ 31 #define CONFIG_SYS_TEXT_BASE 0x80100000 32 33 #define CONFIG_SDRC /* The chip has SDRC controller */ 34 35 #include <asm/arch/cpu.h> /* get chip and board defs */ 36 #include <asm/arch/omap3.h> 37 38 /* Display CPU and Board information */ 39 #define CONFIG_DISPLAY_CPUINFO 40 #define CONFIG_DISPLAY_BOARDINFO 41 42 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_ZERO_BOOTDELAY_CHECK 44 45 /* Clock Defines */ 46 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_SCLK (V_OSCK >> 1) 48 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_SETUP_MEMORY_TAGS 53 #define CONFIG_INITRD_TAG 54 #define CONFIG_REVISION_TAG 55 56 #define CONFIG_OF_LIBFDT 57 58 /* Size of malloc() pool */ 59 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 60 61 /* Hardware drivers */ 62 63 /* GPIO support */ 64 #define CONFIG_OMAP_GPIO 65 66 /* GPIO banks */ 67 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 68 69 /* LED support */ 70 #define CONFIG_STATUS_LED 71 #define CONFIG_BOARD_SPECIFIC_LED 72 #define CONFIG_CMD_LED /* LED command */ 73 #define STATUS_LED_BIT (1 << 0) 74 #define STATUS_LED_STATE STATUS_LED_ON 75 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 76 #define STATUS_LED_BIT1 (1 << 1) 77 #define STATUS_LED_STATE1 STATUS_LED_ON 78 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 79 #define STATUS_LED_BIT2 (1 << 2) 80 #define STATUS_LED_STATE2 STATUS_LED_ON 81 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 82 83 /* NS16550 Configuration */ 84 #define CONFIG_SYS_NS16550 85 #define CONFIG_SYS_NS16550_SERIAL 86 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 87 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 88 89 /* select serial console configuration */ 90 #define CONFIG_CONS_INDEX 3 91 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 92 #define CONFIG_SERIAL3 3 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 97 /* MMC */ 98 #define CONFIG_GENERIC_MMC 99 #define CONFIG_MMC 100 #define CONFIG_OMAP_HSMMC 101 #define CONFIG_DOS_PARTITION 102 103 /* I2C */ 104 #define CONFIG_SYS_I2C 105 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 106 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 107 #define CONFIG_SYS_I2C_OMAP34XX 108 109 110 /* EEPROM */ 111 #define CONFIG_SYS_I2C_MULTI_EEPROMS 112 #define CONFIG_CMD_EEPROM 113 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 114 #define CONFIG_SYS_EEPROM_BUS_NUM 1 115 116 /* TWL4030 */ 117 #define CONFIG_TWL4030_POWER 118 #define CONFIG_TWL4030_LED 119 120 /* Board NAND Info */ 121 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 122 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 123 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 124 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 125 "128k(SPL)," \ 126 "1m(u-boot)," \ 127 "384k(u-boot-env1)," \ 128 "1152k(mtdoops)," \ 129 "384k(u-boot-env2)," \ 130 "5m(kernel)," \ 131 "2m(fdt)," \ 132 "-(ubi)" 133 134 #define CONFIG_NAND_OMAP_GPMC 135 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 136 /* to access nand */ 137 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 138 /* to access nand at */ 139 /* CS0 */ 140 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 141 /* devices */ 142 #define CONFIG_BCH 143 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 144 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 145 146 /* commands to include */ 147 #include <config_cmd_default.h> 148 149 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 150 #define CONFIG_CMD_FAT /* FAT support */ 151 #define CONFIG_CMD_I2C /* I2C serial bus support */ 152 #define CONFIG_CMD_MMC /* MMC support */ 153 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 154 #define CONFIG_CMD_NAND /* NAND support */ 155 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 156 #define CONFIG_CMD_UBI /* UBI commands */ 157 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 158 #define CONFIG_LZO /* LZO is needed for UBIFS */ 159 160 #undef CONFIG_CMD_NET 161 #undef CONFIG_CMD_NFS 162 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 163 #undef CONFIG_CMD_IMI /* iminfo */ 164 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 165 166 /* needed for ubi */ 167 #define CONFIG_RBTREE 168 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 169 #define CONFIG_MTD_PARTITIONS 170 171 /* Environment information (this is the common part) */ 172 173 #define CONFIG_BOOTDELAY 0 174 175 /* hang() the board on panic() */ 176 #define CONFIG_PANIC_HANG 177 178 /* environment placement (for NAND), is different for FLASHCARD but does not 179 * harm there */ 180 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 181 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 182 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 183 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 184 185 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 186 * value can not be used here! */ 187 #define CONFIG_LOADADDR 0x82000000 188 189 #define CONFIG_COMMON_ENV_SETTINGS \ 190 "console=ttyO2,115200n8\0" \ 191 "mmcdev=0\0" \ 192 "vram=3M\0" \ 193 "defaultdisplay=lcd\0" \ 194 "kernelopts=mtdoops.mtddev=3\0" \ 195 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 196 "mtdids=" MTDIDS_DEFAULT "\0" \ 197 "commonargs=" \ 198 "setenv bootargs console=${console} " \ 199 "${mtdparts} " \ 200 "${kernelopts} " \ 201 "vt.global_cursor_default=0 " \ 202 "vram=${vram} " \ 203 "omapdss.def_disp=${defaultdisplay}\0" 204 205 #define CONFIG_BOOTCOMMAND "run autoboot" 206 207 /* specific environment settings for different use cases 208 * FLASHCARD: used to run a rdimage from sdcard to program the device 209 * 'NORMAL': used to boot kernel from sdcard, nand, ... 210 * 211 * The main aim for the FLASHCARD skin is to have an embedded environment 212 * which will not be influenced by any data already on the device. 213 */ 214 #ifdef CONFIG_FLASHCARD 215 216 #define CONFIG_ENV_IS_NOWHERE 217 218 /* the rdaddr is 16 MiB before the loadaddr */ 219 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 220 221 #define CONFIG_EXTRA_ENV_SETTINGS \ 222 CONFIG_COMMON_ENV_SETTINGS \ 223 CONFIG_ENV_RDADDR \ 224 "autoboot=" \ 225 "run commonargs; " \ 226 "setenv bootargs ${bootargs} " \ 227 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 228 "rdinit=/sbin/init; " \ 229 "mmc dev ${mmcdev}; mmc rescan; " \ 230 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 231 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 232 "bootm ${loadaddr} ${rdaddr}\0" 233 234 #else /* CONFIG_FLASHCARD */ 235 236 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 237 238 #define CONFIG_ENV_IS_IN_NAND 239 240 #define CONFIG_EXTRA_ENV_SETTINGS \ 241 CONFIG_COMMON_ENV_SETTINGS \ 242 "mmcargs=" \ 243 "run commonargs; " \ 244 "setenv bootargs ${bootargs} " \ 245 "root=/dev/mmcblk0p2 " \ 246 "rootwait " \ 247 "rw\0" \ 248 "nandargs=" \ 249 "run commonargs; " \ 250 "setenv bootargs ${bootargs} " \ 251 "root=ubi0:root " \ 252 "ubi.mtd=7 " \ 253 "rootfstype=ubifs " \ 254 "ro\0" \ 255 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 256 "bootscript=echo Running bootscript from mmc ...; " \ 257 "source ${loadaddr}\0" \ 258 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 259 "mmcboot=echo Booting from mmc ...; " \ 260 "run mmcargs; " \ 261 "bootm ${loadaddr}\0" \ 262 "loaduimage_ubi=ubi part ubi; " \ 263 "ubifsmount ubi:root; " \ 264 "ubifsload ${loadaddr} /boot/uImage\0" \ 265 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 266 "nandboot=echo Booting from nand ...; " \ 267 "run nandargs; " \ 268 "run loaduimage_nand; " \ 269 "bootm ${loadaddr}\0" \ 270 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 271 "if run loadbootscript; then " \ 272 "run bootscript; " \ 273 "else " \ 274 "if run loaduimage; then " \ 275 "run mmcboot; " \ 276 "else run nandboot; " \ 277 "fi; " \ 278 "fi; " \ 279 "else run nandboot; fi\0" 280 281 #endif /* CONFIG_FLASHCARD */ 282 283 /* Miscellaneous configurable options */ 284 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 285 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 286 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 287 #define CONFIG_AUTO_COMPLETE 288 #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " 289 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 290 /* Print Buffer Size */ 291 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 292 sizeof(CONFIG_SYS_PROMPT) + 16) 293 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 294 295 /* Boot Argument Buffer Size */ 296 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 297 298 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 299 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 300 0x07000000) /* 112 MB */ 301 302 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 303 304 /* 305 * OMAP3 has 12 GP timers, they can be driven by the system clock 306 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 307 * This rate is divided by a local divisor. 308 */ 309 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 310 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 311 312 /* Physical Memory Map */ 313 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 314 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 315 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 316 317 /* NAND and environment organization */ 318 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 319 320 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 321 322 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 323 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 324 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 325 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 326 CONFIG_SYS_INIT_RAM_SIZE - \ 327 GENERATED_GBL_DATA_SIZE) 328 329 /* SRAM config */ 330 #define CONFIG_SYS_SRAM_START 0x40200000 331 #define CONFIG_SYS_SRAM_SIZE 0x10000 332 333 /* Defines for SPL */ 334 #define CONFIG_SPL 335 #define CONFIG_SPL_FRAMEWORK 336 #define CONFIG_SPL_NAND_SIMPLE 337 338 #define CONFIG_SPL_BOARD_INIT 339 #define CONFIG_SPL_GPIO_SUPPORT 340 #define CONFIG_SPL_LIBCOMMON_SUPPORT 341 #define CONFIG_SPL_LIBDISK_SUPPORT 342 #define CONFIG_SPL_I2C_SUPPORT 343 #define CONFIG_SPL_LIBGENERIC_SUPPORT 344 #define CONFIG_SPL_SERIAL_SUPPORT 345 #define CONFIG_SPL_POWER_SUPPORT 346 #define CONFIG_SPL_NAND_SUPPORT 347 #define CONFIG_SPL_NAND_BASE 348 #define CONFIG_SPL_NAND_DRIVERS 349 #define CONFIG_SPL_NAND_ECC 350 #define CONFIG_SPL_MMC_SUPPORT 351 #define CONFIG_SPL_FAT_SUPPORT 352 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 353 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 354 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 355 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 356 357 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 358 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ 359 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 360 361 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 362 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 363 364 /* NAND boot config */ 365 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 366 #define CONFIG_SYS_NAND_PAGE_COUNT 64 367 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 368 #define CONFIG_SYS_NAND_OOBSIZE 64 369 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 370 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 371 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 372 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 373 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 374 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 375 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 376 52, 53, 54, 55, 56} 377 378 #define CONFIG_SYS_NAND_ECCSIZE 512 379 #define CONFIG_SYS_NAND_ECCBYTES 13 380 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 381 382 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 383 384 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 385 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 386 387 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 388 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 389 390 #define CONFIG_SYS_ALT_MEMTEST 391 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 392 #endif /* __CONFIG_H */ 393