1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_SYS_CACHELINE_SIZE 64 20 21 /* High Level Configuration Options */ 22 #define CONFIG_SYS_THUMB_BUILD 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_COMMON 25 /* Common ARM Erratas */ 26 #define CONFIG_ARM_ERRATA_454179 27 #define CONFIG_ARM_ERRATA_430973 28 #define CONFIG_ARM_ERRATA_621766 29 30 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 31 /* 32 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 33 * 64 bytes before this address should be set aside for u-boot.img's 34 * header. That is 0x800FFFC0--0x80100000 should not be used for any 35 * other needs. 36 */ 37 #define CONFIG_SYS_TEXT_BASE 0x80100000 38 39 #define CONFIG_SDRC /* The chip has SDRC controller */ 40 41 #include <asm/arch/cpu.h> /* get chip and board defs */ 42 #include <asm/arch/omap.h> 43 44 /* Display CPU and Board information */ 45 #define CONFIG_DISPLAY_CPUINFO 46 #define CONFIG_DISPLAY_BOARDINFO 47 48 #define CONFIG_SILENT_CONSOLE 49 #define CONFIG_ZERO_BOOTDELAY_CHECK 50 51 /* Clock Defines */ 52 #define V_OSCK 26000000 /* Clock output from T2 */ 53 #define V_SCLK (V_OSCK >> 1) 54 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 58 #define CONFIG_SETUP_MEMORY_TAGS 59 #define CONFIG_INITRD_TAG 60 #define CONFIG_REVISION_TAG 61 62 /* Size of malloc() pool */ 63 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 64 65 /* Hardware drivers */ 66 67 /* GPIO support */ 68 #define CONFIG_OMAP_GPIO 69 70 /* GPIO banks */ 71 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 72 73 /* LED support */ 74 #define CONFIG_STATUS_LED 75 #define CONFIG_BOARD_SPECIFIC_LED 76 #define CONFIG_CMD_LED /* LED command */ 77 #define STATUS_LED_BIT (1 << 0) 78 #define STATUS_LED_STATE STATUS_LED_ON 79 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 80 #define STATUS_LED_BIT1 (1 << 1) 81 #define STATUS_LED_STATE1 STATUS_LED_ON 82 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 83 #define STATUS_LED_BIT2 (1 << 2) 84 #define STATUS_LED_STATE2 STATUS_LED_ON 85 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 86 87 /* NS16550 Configuration */ 88 #define CONFIG_SYS_NS16550_SERIAL 89 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 90 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 91 92 /* select serial console configuration */ 93 #define CONFIG_CONS_INDEX 3 94 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 95 #define CONFIG_SERIAL3 3 96 #define CONFIG_BAUDRATE 115200 97 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 98 115200} 99 100 /* MMC */ 101 #define CONFIG_GENERIC_MMC 102 #define CONFIG_MMC 103 #define CONFIG_OMAP_HSMMC 104 #define CONFIG_DOS_PARTITION 105 106 /* I2C */ 107 #define CONFIG_SYS_I2C 108 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 109 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 110 #define CONFIG_SYS_I2C_OMAP34XX 111 112 113 /* EEPROM */ 114 #define CONFIG_CMD_EEPROM 115 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 116 #define CONFIG_SYS_EEPROM_BUS_NUM 1 117 118 /* TWL4030 */ 119 #define CONFIG_TWL4030_POWER 120 #define CONFIG_TWL4030_LED 121 122 /* Board NAND Info */ 123 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 124 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 125 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 126 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 127 "128k(SPL)," \ 128 "1m(u-boot)," \ 129 "384k(u-boot-env1)," \ 130 "1152k(mtdoops)," \ 131 "384k(u-boot-env2)," \ 132 "5m(kernel)," \ 133 "2m(fdt)," \ 134 "-(ubi)" 135 136 #define CONFIG_NAND_OMAP_GPMC 137 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 138 /* to access nand */ 139 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 140 /* to access nand at */ 141 /* CS0 */ 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 143 /* devices */ 144 #define CONFIG_BCH 145 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 146 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 147 148 /* commands to include */ 149 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 150 #define CONFIG_CMD_NAND /* NAND support */ 151 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 152 #define CONFIG_CMD_UBI /* UBI commands */ 153 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 154 #define CONFIG_LZO /* LZO is needed for UBIFS */ 155 156 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 157 158 /* needed for ubi */ 159 #define CONFIG_RBTREE 160 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 161 #define CONFIG_MTD_PARTITIONS 162 163 /* Environment information (this is the common part) */ 164 165 #define CONFIG_BOOTDELAY 0 166 167 /* hang() the board on panic() */ 168 #define CONFIG_PANIC_HANG 169 170 /* environment placement (for NAND), is different for FLASHCARD but does not 171 * harm there */ 172 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 173 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 174 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 175 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 176 177 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 178 * value can not be used here! */ 179 #define CONFIG_LOADADDR 0x82000000 180 181 #define CONFIG_COMMON_ENV_SETTINGS \ 182 "console=ttyO2,115200n8\0" \ 183 "mmcdev=0\0" \ 184 "vram=3M\0" \ 185 "defaultdisplay=lcd\0" \ 186 "kernelopts=mtdoops.mtddev=3\0" \ 187 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 188 "mtdids=" MTDIDS_DEFAULT "\0" \ 189 "commonargs=" \ 190 "setenv bootargs console=${console} " \ 191 "${mtdparts} " \ 192 "${kernelopts} " \ 193 "vt.global_cursor_default=0 " \ 194 "vram=${vram} " \ 195 "omapdss.def_disp=${defaultdisplay}\0" 196 197 #define CONFIG_BOOTCOMMAND "run autoboot" 198 199 /* specific environment settings for different use cases 200 * FLASHCARD: used to run a rdimage from sdcard to program the device 201 * 'NORMAL': used to boot kernel from sdcard, nand, ... 202 * 203 * The main aim for the FLASHCARD skin is to have an embedded environment 204 * which will not be influenced by any data already on the device. 205 */ 206 #ifdef CONFIG_FLASHCARD 207 208 #define CONFIG_ENV_IS_NOWHERE 209 210 /* the rdaddr is 16 MiB before the loadaddr */ 211 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 212 213 #define CONFIG_EXTRA_ENV_SETTINGS \ 214 CONFIG_COMMON_ENV_SETTINGS \ 215 CONFIG_ENV_RDADDR \ 216 "autoboot=" \ 217 "run commonargs; " \ 218 "setenv bootargs ${bootargs} " \ 219 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 220 "rdinit=/sbin/init; " \ 221 "mmc dev ${mmcdev}; mmc rescan; " \ 222 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 223 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 224 "bootm ${loadaddr} ${rdaddr}\0" 225 226 #else /* CONFIG_FLASHCARD */ 227 228 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 229 230 #define CONFIG_ENV_IS_IN_NAND 231 232 #define CONFIG_EXTRA_ENV_SETTINGS \ 233 CONFIG_COMMON_ENV_SETTINGS \ 234 "mmcargs=" \ 235 "run commonargs; " \ 236 "setenv bootargs ${bootargs} " \ 237 "root=/dev/mmcblk0p2 " \ 238 "rootwait " \ 239 "rw\0" \ 240 "nandargs=" \ 241 "run commonargs; " \ 242 "setenv bootargs ${bootargs} " \ 243 "root=ubi0:root " \ 244 "ubi.mtd=7 " \ 245 "rootfstype=ubifs " \ 246 "ro\0" \ 247 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 248 "bootscript=echo Running bootscript from mmc ...; " \ 249 "source ${loadaddr}\0" \ 250 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 251 "mmcboot=echo Booting from mmc ...; " \ 252 "run mmcargs; " \ 253 "bootm ${loadaddr}\0" \ 254 "loaduimage_ubi=ubi part ubi; " \ 255 "ubifsmount ubi:root; " \ 256 "ubifsload ${loadaddr} /boot/uImage\0" \ 257 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 258 "nandboot=echo Booting from nand ...; " \ 259 "run nandargs; " \ 260 "run loaduimage_nand; " \ 261 "bootm ${loadaddr}\0" \ 262 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 263 "if run loadbootscript; then " \ 264 "run bootscript; " \ 265 "else " \ 266 "if run loaduimage; then " \ 267 "run mmcboot; " \ 268 "else run nandboot; " \ 269 "fi; " \ 270 "fi; " \ 271 "else run nandboot; fi\0" 272 273 #endif /* CONFIG_FLASHCARD */ 274 275 /* Miscellaneous configurable options */ 276 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 277 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 278 #define CONFIG_AUTO_COMPLETE 279 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 280 /* Print Buffer Size */ 281 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 282 sizeof(CONFIG_SYS_PROMPT) + 16) 283 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 284 285 /* Boot Argument Buffer Size */ 286 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 287 288 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 289 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 290 0x07000000) /* 112 MB */ 291 292 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 293 294 /* 295 * OMAP3 has 12 GP timers, they can be driven by the system clock 296 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 297 * This rate is divided by a local divisor. 298 */ 299 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 300 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 301 302 /* Physical Memory Map */ 303 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 304 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 305 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 306 307 /* NAND and environment organization */ 308 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 309 310 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 311 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 312 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 313 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 314 CONFIG_SYS_INIT_RAM_SIZE - \ 315 GENERATED_GBL_DATA_SIZE) 316 317 /* SRAM config */ 318 #define CONFIG_SYS_SRAM_START 0x40200000 319 #define CONFIG_SYS_SRAM_SIZE 0x10000 320 321 /* Defines for SPL */ 322 #define CONFIG_SPL_FRAMEWORK 323 #define CONFIG_SPL_NAND_SIMPLE 324 325 #define CONFIG_SPL_BOARD_INIT 326 #define CONFIG_SPL_GPIO_SUPPORT 327 #define CONFIG_SPL_LIBCOMMON_SUPPORT 328 #define CONFIG_SPL_LIBDISK_SUPPORT 329 #define CONFIG_SPL_I2C_SUPPORT 330 #define CONFIG_SPL_LIBGENERIC_SUPPORT 331 #define CONFIG_SPL_SERIAL_SUPPORT 332 #define CONFIG_SPL_POWER_SUPPORT 333 #define CONFIG_SPL_NAND_SUPPORT 334 #define CONFIG_SPL_NAND_BASE 335 #define CONFIG_SPL_NAND_DRIVERS 336 #define CONFIG_SPL_NAND_ECC 337 #define CONFIG_SPL_MMC_SUPPORT 338 #define CONFIG_SPL_FAT_SUPPORT 339 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 340 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 341 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 342 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 343 344 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 345 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ 346 347 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 348 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 349 350 /* NAND boot config */ 351 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 352 #define CONFIG_SYS_NAND_PAGE_COUNT 64 353 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 354 #define CONFIG_SYS_NAND_OOBSIZE 64 355 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 356 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 357 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 358 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 359 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 360 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 361 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 362 52, 53, 54, 55, 56} 363 364 #define CONFIG_SYS_NAND_ECCSIZE 512 365 #define CONFIG_SYS_NAND_ECCBYTES 13 366 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 367 368 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 369 370 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 371 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 372 373 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 374 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 375 376 #define CONFIG_SYS_ALT_MEMTEST 377 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 378 #endif /* __CONFIG_H */ 379