1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_OMAP /* in a TI OMAP core */ 21 #define CONFIG_OMAP_COMMON 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 28 /* 29 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 30 * 64 bytes before this address should be set aside for u-boot.img's 31 * header. That is 0x800FFFC0--0x80100000 should not be used for any 32 * other needs. 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0x80100000 35 36 #define CONFIG_SDRC /* The chip has SDRC controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap.h> 40 41 #define CONFIG_SYS_GENERIC_BOARD 42 43 /* Display CPU and Board information */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 #define CONFIG_SILENT_CONSOLE 48 #define CONFIG_ZERO_BOOTDELAY_CHECK 49 50 /* Clock Defines */ 51 #define V_OSCK 26000000 /* Clock output from T2 */ 52 #define V_SCLK (V_OSCK >> 1) 53 54 #define CONFIG_MISC_INIT_R 55 56 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 57 #define CONFIG_SETUP_MEMORY_TAGS 58 #define CONFIG_INITRD_TAG 59 #define CONFIG_REVISION_TAG 60 61 #define CONFIG_OF_LIBFDT 62 63 /* Size of malloc() pool */ 64 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 65 66 /* Hardware drivers */ 67 68 /* GPIO support */ 69 #define CONFIG_OMAP_GPIO 70 71 /* GPIO banks */ 72 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 73 74 /* LED support */ 75 #define CONFIG_STATUS_LED 76 #define CONFIG_BOARD_SPECIFIC_LED 77 #define CONFIG_CMD_LED /* LED command */ 78 #define STATUS_LED_BIT (1 << 0) 79 #define STATUS_LED_STATE STATUS_LED_ON 80 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 81 #define STATUS_LED_BIT1 (1 << 1) 82 #define STATUS_LED_STATE1 STATUS_LED_ON 83 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 84 #define STATUS_LED_BIT2 (1 << 2) 85 #define STATUS_LED_STATE2 STATUS_LED_ON 86 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 87 88 /* NS16550 Configuration */ 89 #define CONFIG_SYS_NS16550 90 #define CONFIG_SYS_NS16550_SERIAL 91 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 92 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 93 94 /* select serial console configuration */ 95 #define CONFIG_CONS_INDEX 3 96 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 97 #define CONFIG_SERIAL3 3 98 #define CONFIG_BAUDRATE 115200 99 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 100 115200} 101 102 /* MMC */ 103 #define CONFIG_GENERIC_MMC 104 #define CONFIG_MMC 105 #define CONFIG_OMAP_HSMMC 106 #define CONFIG_DOS_PARTITION 107 108 /* I2C */ 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 111 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 112 #define CONFIG_SYS_I2C_OMAP34XX 113 114 115 /* EEPROM */ 116 #define CONFIG_SYS_I2C_MULTI_EEPROMS 117 #define CONFIG_CMD_EEPROM 118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 119 #define CONFIG_SYS_EEPROM_BUS_NUM 1 120 121 /* TWL4030 */ 122 #define CONFIG_TWL4030_POWER 123 #define CONFIG_TWL4030_LED 124 125 /* Board NAND Info */ 126 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 127 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 128 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 129 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 130 "128k(SPL)," \ 131 "1m(u-boot)," \ 132 "384k(u-boot-env1)," \ 133 "1152k(mtdoops)," \ 134 "384k(u-boot-env2)," \ 135 "5m(kernel)," \ 136 "2m(fdt)," \ 137 "-(ubi)" 138 139 #define CONFIG_NAND_OMAP_GPMC 140 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 141 /* to access nand */ 142 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 143 /* to access nand at */ 144 /* CS0 */ 145 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 146 /* devices */ 147 #define CONFIG_BCH 148 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 149 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 150 151 /* commands to include */ 152 #include <config_cmd_default.h> 153 154 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 155 #define CONFIG_CMD_FAT /* FAT support */ 156 #define CONFIG_CMD_I2C /* I2C serial bus support */ 157 #define CONFIG_CMD_MMC /* MMC support */ 158 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 159 #define CONFIG_CMD_NAND /* NAND support */ 160 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 161 #define CONFIG_CMD_UBI /* UBI commands */ 162 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 163 #define CONFIG_LZO /* LZO is needed for UBIFS */ 164 165 #undef CONFIG_CMD_NFS 166 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 167 #undef CONFIG_CMD_IMI /* iminfo */ 168 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 169 170 /* needed for ubi */ 171 #define CONFIG_RBTREE 172 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 173 #define CONFIG_MTD_PARTITIONS 174 175 /* Environment information (this is the common part) */ 176 177 #define CONFIG_BOOTDELAY 0 178 179 /* hang() the board on panic() */ 180 #define CONFIG_PANIC_HANG 181 182 /* environment placement (for NAND), is different for FLASHCARD but does not 183 * harm there */ 184 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 185 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 186 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 187 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 188 189 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 190 * value can not be used here! */ 191 #define CONFIG_LOADADDR 0x82000000 192 193 #define CONFIG_COMMON_ENV_SETTINGS \ 194 "console=ttyO2,115200n8\0" \ 195 "mmcdev=0\0" \ 196 "vram=3M\0" \ 197 "defaultdisplay=lcd\0" \ 198 "kernelopts=mtdoops.mtddev=3\0" \ 199 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 200 "mtdids=" MTDIDS_DEFAULT "\0" \ 201 "commonargs=" \ 202 "setenv bootargs console=${console} " \ 203 "${mtdparts} " \ 204 "${kernelopts} " \ 205 "vt.global_cursor_default=0 " \ 206 "vram=${vram} " \ 207 "omapdss.def_disp=${defaultdisplay}\0" 208 209 #define CONFIG_BOOTCOMMAND "run autoboot" 210 211 /* specific environment settings for different use cases 212 * FLASHCARD: used to run a rdimage from sdcard to program the device 213 * 'NORMAL': used to boot kernel from sdcard, nand, ... 214 * 215 * The main aim for the FLASHCARD skin is to have an embedded environment 216 * which will not be influenced by any data already on the device. 217 */ 218 #ifdef CONFIG_FLASHCARD 219 220 #define CONFIG_ENV_IS_NOWHERE 221 222 /* the rdaddr is 16 MiB before the loadaddr */ 223 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 224 225 #define CONFIG_EXTRA_ENV_SETTINGS \ 226 CONFIG_COMMON_ENV_SETTINGS \ 227 CONFIG_ENV_RDADDR \ 228 "autoboot=" \ 229 "run commonargs; " \ 230 "setenv bootargs ${bootargs} " \ 231 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 232 "rdinit=/sbin/init; " \ 233 "mmc dev ${mmcdev}; mmc rescan; " \ 234 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 235 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 236 "bootm ${loadaddr} ${rdaddr}\0" 237 238 #else /* CONFIG_FLASHCARD */ 239 240 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 241 242 #define CONFIG_ENV_IS_IN_NAND 243 244 #define CONFIG_EXTRA_ENV_SETTINGS \ 245 CONFIG_COMMON_ENV_SETTINGS \ 246 "mmcargs=" \ 247 "run commonargs; " \ 248 "setenv bootargs ${bootargs} " \ 249 "root=/dev/mmcblk0p2 " \ 250 "rootwait " \ 251 "rw\0" \ 252 "nandargs=" \ 253 "run commonargs; " \ 254 "setenv bootargs ${bootargs} " \ 255 "root=ubi0:root " \ 256 "ubi.mtd=7 " \ 257 "rootfstype=ubifs " \ 258 "ro\0" \ 259 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 260 "bootscript=echo Running bootscript from mmc ...; " \ 261 "source ${loadaddr}\0" \ 262 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 263 "mmcboot=echo Booting from mmc ...; " \ 264 "run mmcargs; " \ 265 "bootm ${loadaddr}\0" \ 266 "loaduimage_ubi=ubi part ubi; " \ 267 "ubifsmount ubi:root; " \ 268 "ubifsload ${loadaddr} /boot/uImage\0" \ 269 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 270 "nandboot=echo Booting from nand ...; " \ 271 "run nandargs; " \ 272 "run loaduimage_nand; " \ 273 "bootm ${loadaddr}\0" \ 274 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 275 "if run loadbootscript; then " \ 276 "run bootscript; " \ 277 "else " \ 278 "if run loaduimage; then " \ 279 "run mmcboot; " \ 280 "else run nandboot; " \ 281 "fi; " \ 282 "fi; " \ 283 "else run nandboot; fi\0" 284 285 #endif /* CONFIG_FLASHCARD */ 286 287 /* Miscellaneous configurable options */ 288 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 289 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 290 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 291 #define CONFIG_AUTO_COMPLETE 292 #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " 293 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 294 /* Print Buffer Size */ 295 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 296 sizeof(CONFIG_SYS_PROMPT) + 16) 297 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 298 299 /* Boot Argument Buffer Size */ 300 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 301 302 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 303 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 304 0x07000000) /* 112 MB */ 305 306 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 307 308 /* 309 * OMAP3 has 12 GP timers, they can be driven by the system clock 310 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 311 * This rate is divided by a local divisor. 312 */ 313 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 314 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 315 316 /* Physical Memory Map */ 317 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 318 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 319 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 320 321 /* NAND and environment organization */ 322 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 323 324 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 325 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 326 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 327 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 328 CONFIG_SYS_INIT_RAM_SIZE - \ 329 GENERATED_GBL_DATA_SIZE) 330 331 /* SRAM config */ 332 #define CONFIG_SYS_SRAM_START 0x40200000 333 #define CONFIG_SYS_SRAM_SIZE 0x10000 334 335 /* Defines for SPL */ 336 #define CONFIG_SPL_FRAMEWORK 337 #define CONFIG_SPL_NAND_SIMPLE 338 339 #define CONFIG_SPL_BOARD_INIT 340 #define CONFIG_SPL_GPIO_SUPPORT 341 #define CONFIG_SPL_LIBCOMMON_SUPPORT 342 #define CONFIG_SPL_LIBDISK_SUPPORT 343 #define CONFIG_SPL_I2C_SUPPORT 344 #define CONFIG_SPL_LIBGENERIC_SUPPORT 345 #define CONFIG_SPL_SERIAL_SUPPORT 346 #define CONFIG_SPL_POWER_SUPPORT 347 #define CONFIG_SPL_NAND_SUPPORT 348 #define CONFIG_SPL_NAND_BASE 349 #define CONFIG_SPL_NAND_DRIVERS 350 #define CONFIG_SPL_NAND_ECC 351 #define CONFIG_SPL_MMC_SUPPORT 352 #define CONFIG_SPL_FAT_SUPPORT 353 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 354 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 355 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 356 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 357 358 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 359 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ 360 361 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 362 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 363 364 /* NAND boot config */ 365 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 366 #define CONFIG_SYS_NAND_PAGE_COUNT 64 367 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 368 #define CONFIG_SYS_NAND_OOBSIZE 64 369 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 370 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 371 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 372 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 373 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 374 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 375 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 376 52, 53, 54, 55, 56} 377 378 #define CONFIG_SYS_NAND_ECCSIZE 512 379 #define CONFIG_SYS_NAND_ECCBYTES 13 380 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 381 382 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 383 384 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 385 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 386 387 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 388 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 389 390 #define CONFIG_SYS_ALT_MEMTEST 391 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 392 #endif /* __CONFIG_H */ 393