1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006-2008 4 * Texas Instruments. 5 * Richard Woodruff <r-woodruff2@ti.com> 6 * Syed Mohammed Khasim <x0khasim@ti.com> 7 * 8 * (C) Copyright 2012 9 * Corscience GmbH & Co. KG 10 * Thomas Weber <weber@corscience.de> 11 * 12 * Configuration settings for the Tricorder board. 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 19 /* 20 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 21 * 64 bytes before this address should be set aside for u-boot.img's 22 * header. That is 0x800FFFC0--0x80100000 should not be used for any 23 * other needs. 24 */ 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 #include <asm/arch/omap.h> 28 29 /* Clock Defines */ 30 #define V_OSCK 26000000 /* Clock output from T2 */ 31 #define V_SCLK (V_OSCK >> 1) 32 33 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 34 #define CONFIG_SETUP_MEMORY_TAGS 35 #define CONFIG_INITRD_TAG 36 #define CONFIG_REVISION_TAG 37 38 /* Size of malloc() pool */ 39 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 40 41 /* Hardware drivers */ 42 43 /* NS16550 Configuration */ 44 #define CONFIG_SYS_NS16550_SERIAL 45 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 46 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 47 48 /* select serial console configuration */ 49 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 50 #define CONFIG_SERIAL3 3 51 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 52 115200} 53 54 /* I2C */ 55 #define CONFIG_SYS_I2C 56 57 58 /* EEPROM */ 59 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 60 #define CONFIG_SYS_EEPROM_BUS_NUM 1 61 62 /* TWL4030 */ 63 #define CONFIG_TWL4030_LED 64 65 /* Board NAND Info */ 66 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 67 /* to access nand at */ 68 /* CS0 */ 69 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 70 /* devices */ 71 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 72 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 73 74 /* needed for ubi */ 75 76 /* Environment information (this is the common part) */ 77 78 79 /* hang() the board on panic() */ 80 81 /* environment placement (for NAND), is different for FLASHCARD but does not 82 * harm there */ 83 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 84 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 85 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 86 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 87 88 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 89 * value can not be used here! */ 90 #define CONFIG_LOADADDR 0x82000000 91 92 #define CONFIG_COMMON_ENV_SETTINGS \ 93 "console=ttyO2,115200n8\0" \ 94 "mmcdev=0\0" \ 95 "vram=3M\0" \ 96 "defaultdisplay=lcd\0" \ 97 "kernelopts=mtdoops.mtddev=3\0" \ 98 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 99 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 100 "commonargs=" \ 101 "setenv bootargs console=${console} " \ 102 "${mtdparts} " \ 103 "${kernelopts} " \ 104 "vt.global_cursor_default=0 " \ 105 "vram=${vram} " \ 106 "omapdss.def_disp=${defaultdisplay}\0" 107 108 #define CONFIG_BOOTCOMMAND "run autoboot" 109 110 /* specific environment settings for different use cases 111 * FLASHCARD: used to run a rdimage from sdcard to program the device 112 * 'NORMAL': used to boot kernel from sdcard, nand, ... 113 * 114 * The main aim for the FLASHCARD skin is to have an embedded environment 115 * which will not be influenced by any data already on the device. 116 */ 117 #ifdef CONFIG_FLASHCARD 118 /* the rdaddr is 16 MiB before the loadaddr */ 119 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 120 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 CONFIG_COMMON_ENV_SETTINGS \ 123 CONFIG_ENV_RDADDR \ 124 "autoboot=" \ 125 "run commonargs; " \ 126 "setenv bootargs ${bootargs} " \ 127 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 128 "rdinit=/sbin/init; " \ 129 "mmc dev ${mmcdev}; mmc rescan; " \ 130 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 131 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 132 "bootm ${loadaddr} ${rdaddr}\0" 133 134 #else /* CONFIG_FLASHCARD */ 135 136 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 137 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 CONFIG_COMMON_ENV_SETTINGS \ 140 "mmcargs=" \ 141 "run commonargs; " \ 142 "setenv bootargs ${bootargs} " \ 143 "root=/dev/mmcblk0p2 " \ 144 "rootwait " \ 145 "rw\0" \ 146 "nandargs=" \ 147 "run commonargs; " \ 148 "setenv bootargs ${bootargs} " \ 149 "root=ubi0:root " \ 150 "ubi.mtd=7 " \ 151 "rootfstype=ubifs " \ 152 "ro\0" \ 153 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 154 "bootscript=echo Running bootscript from mmc ...; " \ 155 "source ${loadaddr}\0" \ 156 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 157 "mmcboot=echo Booting from mmc ...; " \ 158 "run mmcargs; " \ 159 "bootm ${loadaddr}\0" \ 160 "loaduimage_ubi=ubi part ubi; " \ 161 "ubifsmount ubi:root; " \ 162 "ubifsload ${loadaddr} /boot/uImage\0" \ 163 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 164 "nandboot=echo Booting from nand ...; " \ 165 "run nandargs; " \ 166 "run loaduimage_nand; " \ 167 "bootm ${loadaddr}\0" \ 168 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 169 "if run loadbootscript; then " \ 170 "run bootscript; " \ 171 "else " \ 172 "if run loaduimage; then " \ 173 "run mmcboot; " \ 174 "else run nandboot; " \ 175 "fi; " \ 176 "fi; " \ 177 "else run nandboot; fi\0" 178 179 #endif /* CONFIG_FLASHCARD */ 180 181 /* Miscellaneous configurable options */ 182 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 183 184 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 185 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 186 0x07000000) /* 112 MB */ 187 188 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 189 190 /* 191 * OMAP3 has 12 GP timers, they can be driven by the system clock 192 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 193 * This rate is divided by a local divisor. 194 */ 195 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 196 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 197 198 /* Physical Memory Map */ 199 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 200 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 201 202 /* NAND and environment organization */ 203 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 204 205 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 206 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 207 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 208 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - \ 210 GENERATED_GBL_DATA_SIZE) 211 212 /* SRAM config */ 213 #define CONFIG_SYS_SRAM_START 0x40200000 214 #define CONFIG_SYS_SRAM_SIZE 0x10000 215 216 /* Defines for SPL */ 217 218 #define CONFIG_SPL_NAND_BASE 219 #define CONFIG_SPL_NAND_DRIVERS 220 #define CONFIG_SPL_NAND_ECC 221 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 222 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 223 224 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 225 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 226 CONFIG_SPL_TEXT_BASE) 227 228 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 229 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 230 231 /* NAND boot config */ 232 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 233 #define CONFIG_SYS_NAND_PAGE_COUNT 64 234 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 235 #define CONFIG_SYS_NAND_OOBSIZE 64 236 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 237 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 238 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 239 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 240 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 241 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 242 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 243 52, 53, 54, 55, 56} 244 245 #define CONFIG_SYS_NAND_ECCSIZE 512 246 #define CONFIG_SYS_NAND_ECCBYTES 13 247 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 248 249 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 250 251 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 252 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 253 254 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 255 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 256 257 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 258 #endif /* __CONFIG_H */ 259