1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_OMAP /* in a TI OMAP core */ 21 #define CONFIG_OMAP_COMMON 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 28 /* 29 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 30 * 64 bytes before this address should be set aside for u-boot.img's 31 * header. That is 0x800FFFC0--0x80100000 should not be used for any 32 * other needs. 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0x80100000 35 36 #define CONFIG_SDRC /* The chip has SDRC controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap.h> 40 41 42 /* Display CPU and Board information */ 43 #define CONFIG_DISPLAY_CPUINFO 44 #define CONFIG_DISPLAY_BOARDINFO 45 46 #define CONFIG_SILENT_CONSOLE 47 #define CONFIG_ZERO_BOOTDELAY_CHECK 48 49 /* Clock Defines */ 50 #define V_OSCK 26000000 /* Clock output from T2 */ 51 #define V_SCLK (V_OSCK >> 1) 52 53 #define CONFIG_MISC_INIT_R 54 55 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 56 #define CONFIG_SETUP_MEMORY_TAGS 57 #define CONFIG_INITRD_TAG 58 #define CONFIG_REVISION_TAG 59 60 #define CONFIG_OF_LIBFDT 61 62 /* Size of malloc() pool */ 63 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 64 65 /* Hardware drivers */ 66 67 /* GPIO support */ 68 #define CONFIG_OMAP_GPIO 69 70 /* GPIO banks */ 71 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 72 73 /* LED support */ 74 #define CONFIG_STATUS_LED 75 #define CONFIG_BOARD_SPECIFIC_LED 76 #define CONFIG_CMD_LED /* LED command */ 77 #define STATUS_LED_BIT (1 << 0) 78 #define STATUS_LED_STATE STATUS_LED_ON 79 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 80 #define STATUS_LED_BIT1 (1 << 1) 81 #define STATUS_LED_STATE1 STATUS_LED_ON 82 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 83 #define STATUS_LED_BIT2 (1 << 2) 84 #define STATUS_LED_STATE2 STATUS_LED_ON 85 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 86 87 /* NS16550 Configuration */ 88 #define CONFIG_SYS_NS16550 89 #define CONFIG_SYS_NS16550_SERIAL 90 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 91 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 92 93 /* select serial console configuration */ 94 #define CONFIG_CONS_INDEX 3 95 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 96 #define CONFIG_SERIAL3 3 97 #define CONFIG_BAUDRATE 115200 98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 99 115200} 100 101 /* MMC */ 102 #define CONFIG_GENERIC_MMC 103 #define CONFIG_MMC 104 #define CONFIG_OMAP_HSMMC 105 #define CONFIG_DOS_PARTITION 106 107 /* I2C */ 108 #define CONFIG_SYS_I2C 109 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 110 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 111 #define CONFIG_SYS_I2C_OMAP34XX 112 113 114 /* EEPROM */ 115 #define CONFIG_SYS_I2C_MULTI_EEPROMS 116 #define CONFIG_CMD_EEPROM 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 118 #define CONFIG_SYS_EEPROM_BUS_NUM 1 119 120 /* TWL4030 */ 121 #define CONFIG_TWL4030_POWER 122 #define CONFIG_TWL4030_LED 123 124 /* Board NAND Info */ 125 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 126 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 127 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 128 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 129 "128k(SPL)," \ 130 "1m(u-boot)," \ 131 "384k(u-boot-env1)," \ 132 "1152k(mtdoops)," \ 133 "384k(u-boot-env2)," \ 134 "5m(kernel)," \ 135 "2m(fdt)," \ 136 "-(ubi)" 137 138 #define CONFIG_NAND_OMAP_GPMC 139 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 140 /* to access nand */ 141 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 142 /* to access nand at */ 143 /* CS0 */ 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 145 /* devices */ 146 #define CONFIG_BCH 147 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 148 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 149 150 /* commands to include */ 151 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 152 #define CONFIG_CMD_FAT /* FAT support */ 153 #define CONFIG_CMD_I2C /* I2C serial bus support */ 154 #define CONFIG_CMD_MMC /* MMC support */ 155 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 156 #define CONFIG_CMD_NAND /* NAND support */ 157 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 158 #define CONFIG_CMD_UBI /* UBI commands */ 159 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 160 #define CONFIG_LZO /* LZO is needed for UBIFS */ 161 162 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 163 164 /* needed for ubi */ 165 #define CONFIG_RBTREE 166 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 167 #define CONFIG_MTD_PARTITIONS 168 169 /* Environment information (this is the common part) */ 170 171 #define CONFIG_BOOTDELAY 0 172 173 /* hang() the board on panic() */ 174 #define CONFIG_PANIC_HANG 175 176 /* environment placement (for NAND), is different for FLASHCARD but does not 177 * harm there */ 178 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 179 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 180 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 181 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 182 183 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 184 * value can not be used here! */ 185 #define CONFIG_LOADADDR 0x82000000 186 187 #define CONFIG_COMMON_ENV_SETTINGS \ 188 "console=ttyO2,115200n8\0" \ 189 "mmcdev=0\0" \ 190 "vram=3M\0" \ 191 "defaultdisplay=lcd\0" \ 192 "kernelopts=mtdoops.mtddev=3\0" \ 193 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 194 "mtdids=" MTDIDS_DEFAULT "\0" \ 195 "commonargs=" \ 196 "setenv bootargs console=${console} " \ 197 "${mtdparts} " \ 198 "${kernelopts} " \ 199 "vt.global_cursor_default=0 " \ 200 "vram=${vram} " \ 201 "omapdss.def_disp=${defaultdisplay}\0" 202 203 #define CONFIG_BOOTCOMMAND "run autoboot" 204 205 /* specific environment settings for different use cases 206 * FLASHCARD: used to run a rdimage from sdcard to program the device 207 * 'NORMAL': used to boot kernel from sdcard, nand, ... 208 * 209 * The main aim for the FLASHCARD skin is to have an embedded environment 210 * which will not be influenced by any data already on the device. 211 */ 212 #ifdef CONFIG_FLASHCARD 213 214 #define CONFIG_ENV_IS_NOWHERE 215 216 /* the rdaddr is 16 MiB before the loadaddr */ 217 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 218 219 #define CONFIG_EXTRA_ENV_SETTINGS \ 220 CONFIG_COMMON_ENV_SETTINGS \ 221 CONFIG_ENV_RDADDR \ 222 "autoboot=" \ 223 "run commonargs; " \ 224 "setenv bootargs ${bootargs} " \ 225 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 226 "rdinit=/sbin/init; " \ 227 "mmc dev ${mmcdev}; mmc rescan; " \ 228 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 229 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 230 "bootm ${loadaddr} ${rdaddr}\0" 231 232 #else /* CONFIG_FLASHCARD */ 233 234 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 235 236 #define CONFIG_ENV_IS_IN_NAND 237 238 #define CONFIG_EXTRA_ENV_SETTINGS \ 239 CONFIG_COMMON_ENV_SETTINGS \ 240 "mmcargs=" \ 241 "run commonargs; " \ 242 "setenv bootargs ${bootargs} " \ 243 "root=/dev/mmcblk0p2 " \ 244 "rootwait " \ 245 "rw\0" \ 246 "nandargs=" \ 247 "run commonargs; " \ 248 "setenv bootargs ${bootargs} " \ 249 "root=ubi0:root " \ 250 "ubi.mtd=7 " \ 251 "rootfstype=ubifs " \ 252 "ro\0" \ 253 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 254 "bootscript=echo Running bootscript from mmc ...; " \ 255 "source ${loadaddr}\0" \ 256 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 257 "mmcboot=echo Booting from mmc ...; " \ 258 "run mmcargs; " \ 259 "bootm ${loadaddr}\0" \ 260 "loaduimage_ubi=ubi part ubi; " \ 261 "ubifsmount ubi:root; " \ 262 "ubifsload ${loadaddr} /boot/uImage\0" \ 263 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 264 "nandboot=echo Booting from nand ...; " \ 265 "run nandargs; " \ 266 "run loaduimage_nand; " \ 267 "bootm ${loadaddr}\0" \ 268 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 269 "if run loadbootscript; then " \ 270 "run bootscript; " \ 271 "else " \ 272 "if run loaduimage; then " \ 273 "run mmcboot; " \ 274 "else run nandboot; " \ 275 "fi; " \ 276 "fi; " \ 277 "else run nandboot; fi\0" 278 279 #endif /* CONFIG_FLASHCARD */ 280 281 /* Miscellaneous configurable options */ 282 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 283 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 284 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 285 #define CONFIG_AUTO_COMPLETE 286 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 287 /* Print Buffer Size */ 288 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 289 sizeof(CONFIG_SYS_PROMPT) + 16) 290 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 291 292 /* Boot Argument Buffer Size */ 293 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 294 295 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 296 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 297 0x07000000) /* 112 MB */ 298 299 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 300 301 /* 302 * OMAP3 has 12 GP timers, they can be driven by the system clock 303 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 304 * This rate is divided by a local divisor. 305 */ 306 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 307 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 308 309 /* Physical Memory Map */ 310 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 311 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 312 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 313 314 /* NAND and environment organization */ 315 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 316 317 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 318 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 319 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 320 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 321 CONFIG_SYS_INIT_RAM_SIZE - \ 322 GENERATED_GBL_DATA_SIZE) 323 324 /* SRAM config */ 325 #define CONFIG_SYS_SRAM_START 0x40200000 326 #define CONFIG_SYS_SRAM_SIZE 0x10000 327 328 /* Defines for SPL */ 329 #define CONFIG_SPL_FRAMEWORK 330 #define CONFIG_SPL_NAND_SIMPLE 331 332 #define CONFIG_SPL_BOARD_INIT 333 #define CONFIG_SPL_GPIO_SUPPORT 334 #define CONFIG_SPL_LIBCOMMON_SUPPORT 335 #define CONFIG_SPL_LIBDISK_SUPPORT 336 #define CONFIG_SPL_I2C_SUPPORT 337 #define CONFIG_SPL_LIBGENERIC_SUPPORT 338 #define CONFIG_SPL_SERIAL_SUPPORT 339 #define CONFIG_SPL_POWER_SUPPORT 340 #define CONFIG_SPL_NAND_SUPPORT 341 #define CONFIG_SPL_NAND_BASE 342 #define CONFIG_SPL_NAND_DRIVERS 343 #define CONFIG_SPL_NAND_ECC 344 #define CONFIG_SPL_MMC_SUPPORT 345 #define CONFIG_SPL_FAT_SUPPORT 346 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 347 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 348 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 349 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 350 351 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 352 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ 353 354 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 355 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 356 357 /* NAND boot config */ 358 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 359 #define CONFIG_SYS_NAND_PAGE_COUNT 64 360 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 361 #define CONFIG_SYS_NAND_OOBSIZE 64 362 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 363 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 364 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 365 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 366 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 367 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 368 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 369 52, 53, 54, 55, 56} 370 371 #define CONFIG_SYS_NAND_ECCSIZE 512 372 #define CONFIG_SYS_NAND_ECCBYTES 13 373 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 374 375 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 376 377 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 378 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 379 380 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 381 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 382 383 #define CONFIG_SYS_ALT_MEMTEST 384 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 385 #endif /* __CONFIG_H */ 386