1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 20 /* 21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 22 * 64 bytes before this address should be set aside for u-boot.img's 23 * header. That is 0x800FFFC0--0x80100000 should not be used for any 24 * other needs. 25 */ 26 #define CONFIG_SYS_TEXT_BASE 0x80100000 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap.h> 30 31 /* Clock Defines */ 32 #define V_OSCK 26000000 /* Clock output from T2 */ 33 #define V_SCLK (V_OSCK >> 1) 34 35 #define CONFIG_MISC_INIT_R 36 37 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 38 #define CONFIG_SETUP_MEMORY_TAGS 39 #define CONFIG_INITRD_TAG 40 #define CONFIG_REVISION_TAG 41 42 /* Size of malloc() pool */ 43 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 44 45 /* Hardware drivers */ 46 47 /* NS16550 Configuration */ 48 #define CONFIG_SYS_NS16550_SERIAL 49 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 50 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 51 52 /* select serial console configuration */ 53 #define CONFIG_CONS_INDEX 3 54 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 55 #define CONFIG_SERIAL3 3 56 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 57 115200} 58 59 /* I2C */ 60 #define CONFIG_SYS_I2C 61 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 62 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 63 64 65 /* EEPROM */ 66 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 67 #define CONFIG_SYS_EEPROM_BUS_NUM 1 68 69 /* TWL4030 */ 70 #define CONFIG_TWL4030_LED 71 72 /* Board NAND Info */ 73 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 74 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 75 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 76 "128k(SPL)," \ 77 "1m(u-boot)," \ 78 "384k(u-boot-env1)," \ 79 "1152k(mtdoops)," \ 80 "384k(u-boot-env2)," \ 81 "5m(kernel)," \ 82 "2m(fdt)," \ 83 "-(ubi)" 84 85 #define CONFIG_NAND_OMAP_GPMC 86 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 87 /* to access nand */ 88 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 89 /* to access nand at */ 90 /* CS0 */ 91 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 92 /* devices */ 93 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 94 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 95 96 /* needed for ubi */ 97 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 98 #define CONFIG_MTD_PARTITIONS 99 100 /* Environment information (this is the common part) */ 101 102 103 /* hang() the board on panic() */ 104 #define CONFIG_PANIC_HANG 105 106 /* environment placement (for NAND), is different for FLASHCARD but does not 107 * harm there */ 108 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 109 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 110 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 111 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 112 113 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 114 * value can not be used here! */ 115 #define CONFIG_LOADADDR 0x82000000 116 117 #define CONFIG_COMMON_ENV_SETTINGS \ 118 "console=ttyO2,115200n8\0" \ 119 "mmcdev=0\0" \ 120 "vram=3M\0" \ 121 "defaultdisplay=lcd\0" \ 122 "kernelopts=mtdoops.mtddev=3\0" \ 123 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 124 "mtdids=" MTDIDS_DEFAULT "\0" \ 125 "commonargs=" \ 126 "setenv bootargs console=${console} " \ 127 "${mtdparts} " \ 128 "${kernelopts} " \ 129 "vt.global_cursor_default=0 " \ 130 "vram=${vram} " \ 131 "omapdss.def_disp=${defaultdisplay}\0" 132 133 #define CONFIG_BOOTCOMMAND "run autoboot" 134 135 /* specific environment settings for different use cases 136 * FLASHCARD: used to run a rdimage from sdcard to program the device 137 * 'NORMAL': used to boot kernel from sdcard, nand, ... 138 * 139 * The main aim for the FLASHCARD skin is to have an embedded environment 140 * which will not be influenced by any data already on the device. 141 */ 142 #ifdef CONFIG_FLASHCARD 143 /* the rdaddr is 16 MiB before the loadaddr */ 144 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 145 146 #define CONFIG_EXTRA_ENV_SETTINGS \ 147 CONFIG_COMMON_ENV_SETTINGS \ 148 CONFIG_ENV_RDADDR \ 149 "autoboot=" \ 150 "run commonargs; " \ 151 "setenv bootargs ${bootargs} " \ 152 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 153 "rdinit=/sbin/init; " \ 154 "mmc dev ${mmcdev}; mmc rescan; " \ 155 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 156 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 157 "bootm ${loadaddr} ${rdaddr}\0" 158 159 #else /* CONFIG_FLASHCARD */ 160 161 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 162 163 #define CONFIG_EXTRA_ENV_SETTINGS \ 164 CONFIG_COMMON_ENV_SETTINGS \ 165 "mmcargs=" \ 166 "run commonargs; " \ 167 "setenv bootargs ${bootargs} " \ 168 "root=/dev/mmcblk0p2 " \ 169 "rootwait " \ 170 "rw\0" \ 171 "nandargs=" \ 172 "run commonargs; " \ 173 "setenv bootargs ${bootargs} " \ 174 "root=ubi0:root " \ 175 "ubi.mtd=7 " \ 176 "rootfstype=ubifs " \ 177 "ro\0" \ 178 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 179 "bootscript=echo Running bootscript from mmc ...; " \ 180 "source ${loadaddr}\0" \ 181 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 182 "mmcboot=echo Booting from mmc ...; " \ 183 "run mmcargs; " \ 184 "bootm ${loadaddr}\0" \ 185 "loaduimage_ubi=ubi part ubi; " \ 186 "ubifsmount ubi:root; " \ 187 "ubifsload ${loadaddr} /boot/uImage\0" \ 188 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 189 "nandboot=echo Booting from nand ...; " \ 190 "run nandargs; " \ 191 "run loaduimage_nand; " \ 192 "bootm ${loadaddr}\0" \ 193 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 194 "if run loadbootscript; then " \ 195 "run bootscript; " \ 196 "else " \ 197 "if run loaduimage; then " \ 198 "run mmcboot; " \ 199 "else run nandboot; " \ 200 "fi; " \ 201 "fi; " \ 202 "else run nandboot; fi\0" 203 204 #endif /* CONFIG_FLASHCARD */ 205 206 /* Miscellaneous configurable options */ 207 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 208 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 209 #define CONFIG_AUTO_COMPLETE 210 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 211 212 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 213 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 214 0x07000000) /* 112 MB */ 215 216 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 217 218 /* 219 * OMAP3 has 12 GP timers, they can be driven by the system clock 220 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 221 * This rate is divided by a local divisor. 222 */ 223 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 224 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 225 226 /* Physical Memory Map */ 227 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 228 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 229 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 230 231 /* NAND and environment organization */ 232 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 233 234 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 235 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 236 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 237 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 238 CONFIG_SYS_INIT_RAM_SIZE - \ 239 GENERATED_GBL_DATA_SIZE) 240 241 /* SRAM config */ 242 #define CONFIG_SYS_SRAM_START 0x40200000 243 #define CONFIG_SYS_SRAM_SIZE 0x10000 244 245 /* Defines for SPL */ 246 #define CONFIG_SPL_FRAMEWORK 247 #define CONFIG_SPL_NAND_SIMPLE 248 249 #define CONFIG_SPL_NAND_BASE 250 #define CONFIG_SPL_NAND_DRIVERS 251 #define CONFIG_SPL_NAND_ECC 252 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 253 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 254 255 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 256 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 257 CONFIG_SPL_TEXT_BASE) 258 259 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 260 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 261 262 /* NAND boot config */ 263 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 264 #define CONFIG_SYS_NAND_PAGE_COUNT 64 265 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 266 #define CONFIG_SYS_NAND_OOBSIZE 64 267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 268 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 269 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 270 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 271 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 272 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 273 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 274 52, 53, 54, 55, 56} 275 276 #define CONFIG_SYS_NAND_ECCSIZE 512 277 #define CONFIG_SYS_NAND_ECCBYTES 13 278 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 279 280 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 281 282 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 283 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 284 285 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 286 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 287 288 #define CONFIG_SYS_ALT_MEMTEST 289 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 290 #endif /* __CONFIG_H */ 291