1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_THUMB_BUILD 21 #define CONFIG_OMAP /* in a TI OMAP core */ 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 /* 28 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 29 * 64 bytes before this address should be set aside for u-boot.img's 30 * header. That is 0x800FFFC0--0x80100000 should not be used for any 31 * other needs. 32 */ 33 #define CONFIG_SYS_TEXT_BASE 0x80100000 34 35 #define CONFIG_SDRC /* The chip has SDRC controller */ 36 37 #include <asm/arch/cpu.h> /* get chip and board defs */ 38 #include <asm/arch/omap.h> 39 40 /* Clock Defines */ 41 #define V_OSCK 26000000 /* Clock output from T2 */ 42 #define V_SCLK (V_OSCK >> 1) 43 44 #define CONFIG_MISC_INIT_R 45 46 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 47 #define CONFIG_SETUP_MEMORY_TAGS 48 #define CONFIG_INITRD_TAG 49 #define CONFIG_REVISION_TAG 50 51 /* Size of malloc() pool */ 52 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 53 54 /* Hardware drivers */ 55 56 /* GPIO support */ 57 #define CONFIG_OMAP_GPIO 58 59 /* GPIO banks */ 60 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 61 62 /* LED support */ 63 #define CONFIG_STATUS_LED 64 #define CONFIG_BOARD_SPECIFIC_LED 65 #define CONFIG_CMD_LED /* LED command */ 66 #define STATUS_LED_BIT (1 << 0) 67 #define STATUS_LED_STATE STATUS_LED_ON 68 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 69 #define STATUS_LED_BIT1 (1 << 1) 70 #define STATUS_LED_STATE1 STATUS_LED_ON 71 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 72 #define STATUS_LED_BIT2 (1 << 2) 73 #define STATUS_LED_STATE2 STATUS_LED_ON 74 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 75 76 /* NS16550 Configuration */ 77 #define CONFIG_SYS_NS16550_SERIAL 78 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 79 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 80 81 /* select serial console configuration */ 82 #define CONFIG_CONS_INDEX 3 83 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 84 #define CONFIG_SERIAL3 3 85 #define CONFIG_BAUDRATE 115200 86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 87 115200} 88 89 /* MMC */ 90 #define CONFIG_GENERIC_MMC 91 #define CONFIG_DOS_PARTITION 92 93 /* I2C */ 94 #define CONFIG_SYS_I2C 95 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 96 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 97 #define CONFIG_SYS_I2C_OMAP34XX 98 99 100 /* EEPROM */ 101 #define CONFIG_CMD_EEPROM 102 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 103 #define CONFIG_SYS_EEPROM_BUS_NUM 1 104 105 /* TWL4030 */ 106 #define CONFIG_TWL4030_POWER 107 #define CONFIG_TWL4030_LED 108 109 /* Board NAND Info */ 110 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 111 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 112 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 113 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 114 "128k(SPL)," \ 115 "1m(u-boot)," \ 116 "384k(u-boot-env1)," \ 117 "1152k(mtdoops)," \ 118 "384k(u-boot-env2)," \ 119 "5m(kernel)," \ 120 "2m(fdt)," \ 121 "-(ubi)" 122 123 #define CONFIG_NAND_OMAP_GPMC 124 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 125 /* to access nand */ 126 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 127 /* to access nand at */ 128 /* CS0 */ 129 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 130 /* devices */ 131 #define CONFIG_BCH 132 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 133 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 134 135 /* commands to include */ 136 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 137 #define CONFIG_CMD_NAND /* NAND support */ 138 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 139 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 140 #define CONFIG_LZO /* LZO is needed for UBIFS */ 141 142 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 143 144 /* needed for ubi */ 145 #define CONFIG_RBTREE 146 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 147 #define CONFIG_MTD_PARTITIONS 148 149 /* Environment information (this is the common part) */ 150 151 152 /* hang() the board on panic() */ 153 #define CONFIG_PANIC_HANG 154 155 /* environment placement (for NAND), is different for FLASHCARD but does not 156 * harm there */ 157 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 158 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 159 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 160 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 161 162 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 163 * value can not be used here! */ 164 #define CONFIG_LOADADDR 0x82000000 165 166 #define CONFIG_COMMON_ENV_SETTINGS \ 167 "console=ttyO2,115200n8\0" \ 168 "mmcdev=0\0" \ 169 "vram=3M\0" \ 170 "defaultdisplay=lcd\0" \ 171 "kernelopts=mtdoops.mtddev=3\0" \ 172 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 173 "mtdids=" MTDIDS_DEFAULT "\0" \ 174 "commonargs=" \ 175 "setenv bootargs console=${console} " \ 176 "${mtdparts} " \ 177 "${kernelopts} " \ 178 "vt.global_cursor_default=0 " \ 179 "vram=${vram} " \ 180 "omapdss.def_disp=${defaultdisplay}\0" 181 182 #define CONFIG_BOOTCOMMAND "run autoboot" 183 184 /* specific environment settings for different use cases 185 * FLASHCARD: used to run a rdimage from sdcard to program the device 186 * 'NORMAL': used to boot kernel from sdcard, nand, ... 187 * 188 * The main aim for the FLASHCARD skin is to have an embedded environment 189 * which will not be influenced by any data already on the device. 190 */ 191 #ifdef CONFIG_FLASHCARD 192 193 #define CONFIG_ENV_IS_NOWHERE 194 195 /* the rdaddr is 16 MiB before the loadaddr */ 196 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 197 198 #define CONFIG_EXTRA_ENV_SETTINGS \ 199 CONFIG_COMMON_ENV_SETTINGS \ 200 CONFIG_ENV_RDADDR \ 201 "autoboot=" \ 202 "run commonargs; " \ 203 "setenv bootargs ${bootargs} " \ 204 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 205 "rdinit=/sbin/init; " \ 206 "mmc dev ${mmcdev}; mmc rescan; " \ 207 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 208 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 209 "bootm ${loadaddr} ${rdaddr}\0" 210 211 #else /* CONFIG_FLASHCARD */ 212 213 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 214 215 #define CONFIG_ENV_IS_IN_NAND 216 217 #define CONFIG_EXTRA_ENV_SETTINGS \ 218 CONFIG_COMMON_ENV_SETTINGS \ 219 "mmcargs=" \ 220 "run commonargs; " \ 221 "setenv bootargs ${bootargs} " \ 222 "root=/dev/mmcblk0p2 " \ 223 "rootwait " \ 224 "rw\0" \ 225 "nandargs=" \ 226 "run commonargs; " \ 227 "setenv bootargs ${bootargs} " \ 228 "root=ubi0:root " \ 229 "ubi.mtd=7 " \ 230 "rootfstype=ubifs " \ 231 "ro\0" \ 232 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 233 "bootscript=echo Running bootscript from mmc ...; " \ 234 "source ${loadaddr}\0" \ 235 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 236 "mmcboot=echo Booting from mmc ...; " \ 237 "run mmcargs; " \ 238 "bootm ${loadaddr}\0" \ 239 "loaduimage_ubi=ubi part ubi; " \ 240 "ubifsmount ubi:root; " \ 241 "ubifsload ${loadaddr} /boot/uImage\0" \ 242 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 243 "nandboot=echo Booting from nand ...; " \ 244 "run nandargs; " \ 245 "run loaduimage_nand; " \ 246 "bootm ${loadaddr}\0" \ 247 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 248 "if run loadbootscript; then " \ 249 "run bootscript; " \ 250 "else " \ 251 "if run loaduimage; then " \ 252 "run mmcboot; " \ 253 "else run nandboot; " \ 254 "fi; " \ 255 "fi; " \ 256 "else run nandboot; fi\0" 257 258 #endif /* CONFIG_FLASHCARD */ 259 260 /* Miscellaneous configurable options */ 261 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 262 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 263 #define CONFIG_AUTO_COMPLETE 264 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 265 /* Print Buffer Size */ 266 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 267 sizeof(CONFIG_SYS_PROMPT) + 16) 268 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 269 270 /* Boot Argument Buffer Size */ 271 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 272 273 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 274 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 275 0x07000000) /* 112 MB */ 276 277 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 278 279 /* 280 * OMAP3 has 12 GP timers, they can be driven by the system clock 281 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 282 * This rate is divided by a local divisor. 283 */ 284 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 285 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 286 287 /* Physical Memory Map */ 288 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 289 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 290 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 291 292 /* NAND and environment organization */ 293 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 294 295 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 296 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 297 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 298 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 299 CONFIG_SYS_INIT_RAM_SIZE - \ 300 GENERATED_GBL_DATA_SIZE) 301 302 /* SRAM config */ 303 #define CONFIG_SYS_SRAM_START 0x40200000 304 #define CONFIG_SYS_SRAM_SIZE 0x10000 305 306 /* Defines for SPL */ 307 #define CONFIG_SPL_FRAMEWORK 308 #define CONFIG_SPL_NAND_SIMPLE 309 310 #define CONFIG_SPL_BOARD_INIT 311 #define CONFIG_SPL_NAND_BASE 312 #define CONFIG_SPL_NAND_DRIVERS 313 #define CONFIG_SPL_NAND_ECC 314 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 315 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 316 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 317 318 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 319 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 320 CONFIG_SPL_TEXT_BASE) 321 322 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 323 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 324 325 /* NAND boot config */ 326 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 327 #define CONFIG_SYS_NAND_PAGE_COUNT 64 328 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 329 #define CONFIG_SYS_NAND_OOBSIZE 64 330 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 331 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 332 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 333 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 334 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 335 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 336 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 337 52, 53, 54, 55, 56} 338 339 #define CONFIG_SYS_NAND_ECCSIZE 512 340 #define CONFIG_SYS_NAND_ECCBYTES 13 341 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 342 343 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 344 345 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 346 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 347 348 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 349 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 350 351 #define CONFIG_SYS_ALT_MEMTEST 352 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 353 #endif /* __CONFIG_H */ 354