1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_THUMB_BUILD 21 #define CONFIG_OMAP /* in a TI OMAP core */ 22 #define CONFIG_OMAP_COMMON 23 /* Common ARM Erratas */ 24 #define CONFIG_ARM_ERRATA_454179 25 #define CONFIG_ARM_ERRATA_430973 26 #define CONFIG_ARM_ERRATA_621766 27 28 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 29 /* 30 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 31 * 64 bytes before this address should be set aside for u-boot.img's 32 * header. That is 0x800FFFC0--0x80100000 should not be used for any 33 * other needs. 34 */ 35 #define CONFIG_SYS_TEXT_BASE 0x80100000 36 37 #define CONFIG_SDRC /* The chip has SDRC controller */ 38 39 #include <asm/arch/cpu.h> /* get chip and board defs */ 40 #include <asm/arch/omap.h> 41 42 /* Display CPU and Board information */ 43 #define CONFIG_DISPLAY_CPUINFO 44 #define CONFIG_DISPLAY_BOARDINFO 45 46 #define CONFIG_SILENT_CONSOLE 47 48 /* Clock Defines */ 49 #define V_OSCK 26000000 /* Clock output from T2 */ 50 #define V_SCLK (V_OSCK >> 1) 51 52 #define CONFIG_MISC_INIT_R 53 54 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 55 #define CONFIG_SETUP_MEMORY_TAGS 56 #define CONFIG_INITRD_TAG 57 #define CONFIG_REVISION_TAG 58 59 /* Size of malloc() pool */ 60 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 61 62 /* Hardware drivers */ 63 64 /* GPIO support */ 65 #define CONFIG_OMAP_GPIO 66 67 /* GPIO banks */ 68 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 69 70 /* LED support */ 71 #define CONFIG_STATUS_LED 72 #define CONFIG_BOARD_SPECIFIC_LED 73 #define CONFIG_CMD_LED /* LED command */ 74 #define STATUS_LED_BIT (1 << 0) 75 #define STATUS_LED_STATE STATUS_LED_ON 76 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 77 #define STATUS_LED_BIT1 (1 << 1) 78 #define STATUS_LED_STATE1 STATUS_LED_ON 79 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 80 #define STATUS_LED_BIT2 (1 << 2) 81 #define STATUS_LED_STATE2 STATUS_LED_ON 82 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 83 84 /* NS16550 Configuration */ 85 #define CONFIG_SYS_NS16550_SERIAL 86 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 87 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 88 89 /* select serial console configuration */ 90 #define CONFIG_CONS_INDEX 3 91 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 92 #define CONFIG_SERIAL3 3 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 97 /* MMC */ 98 #define CONFIG_GENERIC_MMC 99 #define CONFIG_MMC 100 #define CONFIG_OMAP_HSMMC 101 #define CONFIG_DOS_PARTITION 102 103 /* I2C */ 104 #define CONFIG_SYS_I2C 105 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 106 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 107 #define CONFIG_SYS_I2C_OMAP34XX 108 109 110 /* EEPROM */ 111 #define CONFIG_CMD_EEPROM 112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 113 #define CONFIG_SYS_EEPROM_BUS_NUM 1 114 115 /* TWL4030 */ 116 #define CONFIG_TWL4030_POWER 117 #define CONFIG_TWL4030_LED 118 119 /* Board NAND Info */ 120 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 121 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 122 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 123 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 124 "128k(SPL)," \ 125 "1m(u-boot)," \ 126 "384k(u-boot-env1)," \ 127 "1152k(mtdoops)," \ 128 "384k(u-boot-env2)," \ 129 "5m(kernel)," \ 130 "2m(fdt)," \ 131 "-(ubi)" 132 133 #define CONFIG_NAND_OMAP_GPMC 134 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 135 /* to access nand */ 136 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 137 /* to access nand at */ 138 /* CS0 */ 139 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 140 /* devices */ 141 #define CONFIG_BCH 142 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 143 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 144 145 /* commands to include */ 146 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 147 #define CONFIG_CMD_NAND /* NAND support */ 148 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 149 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 150 #define CONFIG_LZO /* LZO is needed for UBIFS */ 151 152 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 153 154 /* needed for ubi */ 155 #define CONFIG_RBTREE 156 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 157 #define CONFIG_MTD_PARTITIONS 158 159 /* Environment information (this is the common part) */ 160 161 162 /* hang() the board on panic() */ 163 #define CONFIG_PANIC_HANG 164 165 /* environment placement (for NAND), is different for FLASHCARD but does not 166 * harm there */ 167 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 168 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 169 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 170 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 171 172 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 173 * value can not be used here! */ 174 #define CONFIG_LOADADDR 0x82000000 175 176 #define CONFIG_COMMON_ENV_SETTINGS \ 177 "console=ttyO2,115200n8\0" \ 178 "mmcdev=0\0" \ 179 "vram=3M\0" \ 180 "defaultdisplay=lcd\0" \ 181 "kernelopts=mtdoops.mtddev=3\0" \ 182 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 183 "mtdids=" MTDIDS_DEFAULT "\0" \ 184 "commonargs=" \ 185 "setenv bootargs console=${console} " \ 186 "${mtdparts} " \ 187 "${kernelopts} " \ 188 "vt.global_cursor_default=0 " \ 189 "vram=${vram} " \ 190 "omapdss.def_disp=${defaultdisplay}\0" 191 192 #define CONFIG_BOOTCOMMAND "run autoboot" 193 194 /* specific environment settings for different use cases 195 * FLASHCARD: used to run a rdimage from sdcard to program the device 196 * 'NORMAL': used to boot kernel from sdcard, nand, ... 197 * 198 * The main aim for the FLASHCARD skin is to have an embedded environment 199 * which will not be influenced by any data already on the device. 200 */ 201 #ifdef CONFIG_FLASHCARD 202 203 #define CONFIG_ENV_IS_NOWHERE 204 205 /* the rdaddr is 16 MiB before the loadaddr */ 206 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 207 208 #define CONFIG_EXTRA_ENV_SETTINGS \ 209 CONFIG_COMMON_ENV_SETTINGS \ 210 CONFIG_ENV_RDADDR \ 211 "autoboot=" \ 212 "run commonargs; " \ 213 "setenv bootargs ${bootargs} " \ 214 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 215 "rdinit=/sbin/init; " \ 216 "mmc dev ${mmcdev}; mmc rescan; " \ 217 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 218 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 219 "bootm ${loadaddr} ${rdaddr}\0" 220 221 #else /* CONFIG_FLASHCARD */ 222 223 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 224 225 #define CONFIG_ENV_IS_IN_NAND 226 227 #define CONFIG_EXTRA_ENV_SETTINGS \ 228 CONFIG_COMMON_ENV_SETTINGS \ 229 "mmcargs=" \ 230 "run commonargs; " \ 231 "setenv bootargs ${bootargs} " \ 232 "root=/dev/mmcblk0p2 " \ 233 "rootwait " \ 234 "rw\0" \ 235 "nandargs=" \ 236 "run commonargs; " \ 237 "setenv bootargs ${bootargs} " \ 238 "root=ubi0:root " \ 239 "ubi.mtd=7 " \ 240 "rootfstype=ubifs " \ 241 "ro\0" \ 242 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 243 "bootscript=echo Running bootscript from mmc ...; " \ 244 "source ${loadaddr}\0" \ 245 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 246 "mmcboot=echo Booting from mmc ...; " \ 247 "run mmcargs; " \ 248 "bootm ${loadaddr}\0" \ 249 "loaduimage_ubi=ubi part ubi; " \ 250 "ubifsmount ubi:root; " \ 251 "ubifsload ${loadaddr} /boot/uImage\0" \ 252 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 253 "nandboot=echo Booting from nand ...; " \ 254 "run nandargs; " \ 255 "run loaduimage_nand; " \ 256 "bootm ${loadaddr}\0" \ 257 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 258 "if run loadbootscript; then " \ 259 "run bootscript; " \ 260 "else " \ 261 "if run loaduimage; then " \ 262 "run mmcboot; " \ 263 "else run nandboot; " \ 264 "fi; " \ 265 "fi; " \ 266 "else run nandboot; fi\0" 267 268 #endif /* CONFIG_FLASHCARD */ 269 270 /* Miscellaneous configurable options */ 271 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 272 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 273 #define CONFIG_AUTO_COMPLETE 274 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 275 /* Print Buffer Size */ 276 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 277 sizeof(CONFIG_SYS_PROMPT) + 16) 278 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 279 280 /* Boot Argument Buffer Size */ 281 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 282 283 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 284 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 285 0x07000000) /* 112 MB */ 286 287 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 288 289 /* 290 * OMAP3 has 12 GP timers, they can be driven by the system clock 291 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 292 * This rate is divided by a local divisor. 293 */ 294 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 295 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 296 297 /* Physical Memory Map */ 298 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 299 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 300 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 301 302 /* NAND and environment organization */ 303 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 304 305 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 306 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 307 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 308 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 309 CONFIG_SYS_INIT_RAM_SIZE - \ 310 GENERATED_GBL_DATA_SIZE) 311 312 /* SRAM config */ 313 #define CONFIG_SYS_SRAM_START 0x40200000 314 #define CONFIG_SYS_SRAM_SIZE 0x10000 315 316 /* Defines for SPL */ 317 #define CONFIG_SPL_FRAMEWORK 318 #define CONFIG_SPL_NAND_SIMPLE 319 320 #define CONFIG_SPL_BOARD_INIT 321 #define CONFIG_SPL_NAND_BASE 322 #define CONFIG_SPL_NAND_DRIVERS 323 #define CONFIG_SPL_NAND_ECC 324 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 325 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 326 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 327 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 328 329 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 330 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 331 CONFIG_SPL_TEXT_BASE) 332 333 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 334 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 335 336 /* NAND boot config */ 337 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 338 #define CONFIG_SYS_NAND_PAGE_COUNT 64 339 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 340 #define CONFIG_SYS_NAND_OOBSIZE 64 341 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 342 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 343 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 344 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 345 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 346 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 347 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 348 52, 53, 54, 55, 56} 349 350 #define CONFIG_SYS_NAND_ECCSIZE 512 351 #define CONFIG_SYS_NAND_ECCBYTES 13 352 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 353 354 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 355 356 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 357 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 358 359 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 360 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 361 362 #define CONFIG_SYS_ALT_MEMTEST 363 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 364 #endif /* __CONFIG_H */ 365