1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 20 /* 21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 22 * 64 bytes before this address should be set aside for u-boot.img's 23 * header. That is 0x800FFFC0--0x80100000 should not be used for any 24 * other needs. 25 */ 26 #define CONFIG_SYS_TEXT_BASE 0x80100000 27 28 #define CONFIG_SDRC /* The chip has SDRC controller */ 29 30 #include <asm/arch/cpu.h> /* get chip and board defs */ 31 #include <asm/arch/omap.h> 32 33 /* Clock Defines */ 34 #define V_OSCK 26000000 /* Clock output from T2 */ 35 #define V_SCLK (V_OSCK >> 1) 36 37 #define CONFIG_MISC_INIT_R 38 39 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 40 #define CONFIG_SETUP_MEMORY_TAGS 41 #define CONFIG_INITRD_TAG 42 #define CONFIG_REVISION_TAG 43 44 /* Size of malloc() pool */ 45 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 46 47 /* Hardware drivers */ 48 49 /* NS16550 Configuration */ 50 #define CONFIG_SYS_NS16550_SERIAL 51 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 52 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 53 54 /* select serial console configuration */ 55 #define CONFIG_CONS_INDEX 3 56 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 57 #define CONFIG_SERIAL3 3 58 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 59 115200} 60 61 /* I2C */ 62 #define CONFIG_SYS_I2C 63 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 64 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 65 #define CONFIG_SYS_I2C_OMAP34XX 66 67 68 /* EEPROM */ 69 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 70 #define CONFIG_SYS_EEPROM_BUS_NUM 1 71 72 /* TWL4030 */ 73 #define CONFIG_TWL4030_LED 74 75 /* Board NAND Info */ 76 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 77 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 78 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 79 "128k(SPL)," \ 80 "1m(u-boot)," \ 81 "384k(u-boot-env1)," \ 82 "1152k(mtdoops)," \ 83 "384k(u-boot-env2)," \ 84 "5m(kernel)," \ 85 "2m(fdt)," \ 86 "-(ubi)" 87 88 #define CONFIG_NAND_OMAP_GPMC 89 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 90 /* to access nand */ 91 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 92 /* to access nand at */ 93 /* CS0 */ 94 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 95 /* devices */ 96 #define CONFIG_BCH 97 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 98 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 99 100 /* commands to include */ 101 #define CONFIG_CMD_NAND /* NAND support */ 102 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 103 104 /* needed for ubi */ 105 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 106 #define CONFIG_MTD_PARTITIONS 107 108 /* Environment information (this is the common part) */ 109 110 111 /* hang() the board on panic() */ 112 #define CONFIG_PANIC_HANG 113 114 /* environment placement (for NAND), is different for FLASHCARD but does not 115 * harm there */ 116 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 117 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 118 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 119 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 120 121 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 122 * value can not be used here! */ 123 #define CONFIG_LOADADDR 0x82000000 124 125 #define CONFIG_COMMON_ENV_SETTINGS \ 126 "console=ttyO2,115200n8\0" \ 127 "mmcdev=0\0" \ 128 "vram=3M\0" \ 129 "defaultdisplay=lcd\0" \ 130 "kernelopts=mtdoops.mtddev=3\0" \ 131 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 132 "mtdids=" MTDIDS_DEFAULT "\0" \ 133 "commonargs=" \ 134 "setenv bootargs console=${console} " \ 135 "${mtdparts} " \ 136 "${kernelopts} " \ 137 "vt.global_cursor_default=0 " \ 138 "vram=${vram} " \ 139 "omapdss.def_disp=${defaultdisplay}\0" 140 141 #define CONFIG_BOOTCOMMAND "run autoboot" 142 143 /* specific environment settings for different use cases 144 * FLASHCARD: used to run a rdimage from sdcard to program the device 145 * 'NORMAL': used to boot kernel from sdcard, nand, ... 146 * 147 * The main aim for the FLASHCARD skin is to have an embedded environment 148 * which will not be influenced by any data already on the device. 149 */ 150 #ifdef CONFIG_FLASHCARD 151 /* the rdaddr is 16 MiB before the loadaddr */ 152 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 153 154 #define CONFIG_EXTRA_ENV_SETTINGS \ 155 CONFIG_COMMON_ENV_SETTINGS \ 156 CONFIG_ENV_RDADDR \ 157 "autoboot=" \ 158 "run commonargs; " \ 159 "setenv bootargs ${bootargs} " \ 160 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 161 "rdinit=/sbin/init; " \ 162 "mmc dev ${mmcdev}; mmc rescan; " \ 163 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 164 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 165 "bootm ${loadaddr} ${rdaddr}\0" 166 167 #else /* CONFIG_FLASHCARD */ 168 169 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 170 171 #define CONFIG_EXTRA_ENV_SETTINGS \ 172 CONFIG_COMMON_ENV_SETTINGS \ 173 "mmcargs=" \ 174 "run commonargs; " \ 175 "setenv bootargs ${bootargs} " \ 176 "root=/dev/mmcblk0p2 " \ 177 "rootwait " \ 178 "rw\0" \ 179 "nandargs=" \ 180 "run commonargs; " \ 181 "setenv bootargs ${bootargs} " \ 182 "root=ubi0:root " \ 183 "ubi.mtd=7 " \ 184 "rootfstype=ubifs " \ 185 "ro\0" \ 186 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 187 "bootscript=echo Running bootscript from mmc ...; " \ 188 "source ${loadaddr}\0" \ 189 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 190 "mmcboot=echo Booting from mmc ...; " \ 191 "run mmcargs; " \ 192 "bootm ${loadaddr}\0" \ 193 "loaduimage_ubi=ubi part ubi; " \ 194 "ubifsmount ubi:root; " \ 195 "ubifsload ${loadaddr} /boot/uImage\0" \ 196 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 197 "nandboot=echo Booting from nand ...; " \ 198 "run nandargs; " \ 199 "run loaduimage_nand; " \ 200 "bootm ${loadaddr}\0" \ 201 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 202 "if run loadbootscript; then " \ 203 "run bootscript; " \ 204 "else " \ 205 "if run loaduimage; then " \ 206 "run mmcboot; " \ 207 "else run nandboot; " \ 208 "fi; " \ 209 "fi; " \ 210 "else run nandboot; fi\0" 211 212 #endif /* CONFIG_FLASHCARD */ 213 214 /* Miscellaneous configurable options */ 215 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 216 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 217 #define CONFIG_AUTO_COMPLETE 218 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 219 /* Print Buffer Size */ 220 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 221 sizeof(CONFIG_SYS_PROMPT) + 16) 222 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 223 224 /* Boot Argument Buffer Size */ 225 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 226 227 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 228 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 229 0x07000000) /* 112 MB */ 230 231 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 232 233 /* 234 * OMAP3 has 12 GP timers, they can be driven by the system clock 235 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 236 * This rate is divided by a local divisor. 237 */ 238 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 239 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 240 241 /* Physical Memory Map */ 242 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 243 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 244 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 245 246 /* NAND and environment organization */ 247 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 248 249 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 250 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 251 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 252 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 253 CONFIG_SYS_INIT_RAM_SIZE - \ 254 GENERATED_GBL_DATA_SIZE) 255 256 /* SRAM config */ 257 #define CONFIG_SYS_SRAM_START 0x40200000 258 #define CONFIG_SYS_SRAM_SIZE 0x10000 259 260 /* Defines for SPL */ 261 #define CONFIG_SPL_FRAMEWORK 262 #define CONFIG_SPL_NAND_SIMPLE 263 264 #define CONFIG_SPL_NAND_BASE 265 #define CONFIG_SPL_NAND_DRIVERS 266 #define CONFIG_SPL_NAND_ECC 267 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 268 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 269 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 270 271 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 272 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 273 CONFIG_SPL_TEXT_BASE) 274 275 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 276 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 277 278 /* NAND boot config */ 279 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 280 #define CONFIG_SYS_NAND_PAGE_COUNT 64 281 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 282 #define CONFIG_SYS_NAND_OOBSIZE 64 283 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 284 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 285 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 286 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 287 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 288 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 289 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 290 52, 53, 54, 55, 56} 291 292 #define CONFIG_SYS_NAND_ECCSIZE 512 293 #define CONFIG_SYS_NAND_ECCBYTES 13 294 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 295 296 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 297 298 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 299 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 300 301 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 302 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 303 304 #define CONFIG_SYS_ALT_MEMTEST 305 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 306 #endif /* __CONFIG_H */ 307