1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_THUMB_BUILD 21 #define CONFIG_OMAP /* in a TI OMAP core */ 22 #define CONFIG_OMAP_COMMON 23 /* Common ARM Erratas */ 24 #define CONFIG_ARM_ERRATA_454179 25 #define CONFIG_ARM_ERRATA_430973 26 #define CONFIG_ARM_ERRATA_621766 27 28 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 29 /* 30 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 31 * 64 bytes before this address should be set aside for u-boot.img's 32 * header. That is 0x800FFFC0--0x80100000 should not be used for any 33 * other needs. 34 */ 35 #define CONFIG_SYS_TEXT_BASE 0x80100000 36 37 #define CONFIG_SDRC /* The chip has SDRC controller */ 38 39 #include <asm/arch/cpu.h> /* get chip and board defs */ 40 #include <asm/arch/omap.h> 41 42 43 /* Display CPU and Board information */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 #define CONFIG_SILENT_CONSOLE 48 #define CONFIG_ZERO_BOOTDELAY_CHECK 49 50 /* Clock Defines */ 51 #define V_OSCK 26000000 /* Clock output from T2 */ 52 #define V_SCLK (V_OSCK >> 1) 53 54 #define CONFIG_MISC_INIT_R 55 56 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 57 #define CONFIG_SETUP_MEMORY_TAGS 58 #define CONFIG_INITRD_TAG 59 #define CONFIG_REVISION_TAG 60 61 #define CONFIG_OF_LIBFDT 62 63 /* Size of malloc() pool */ 64 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 65 66 /* Hardware drivers */ 67 68 /* GPIO support */ 69 #define CONFIG_OMAP_GPIO 70 71 /* GPIO banks */ 72 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 73 74 /* LED support */ 75 #define CONFIG_STATUS_LED 76 #define CONFIG_BOARD_SPECIFIC_LED 77 #define CONFIG_CMD_LED /* LED command */ 78 #define STATUS_LED_BIT (1 << 0) 79 #define STATUS_LED_STATE STATUS_LED_ON 80 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 81 #define STATUS_LED_BIT1 (1 << 1) 82 #define STATUS_LED_STATE1 STATUS_LED_ON 83 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 84 #define STATUS_LED_BIT2 (1 << 2) 85 #define STATUS_LED_STATE2 STATUS_LED_ON 86 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 87 88 /* NS16550 Configuration */ 89 #define CONFIG_SYS_NS16550_SERIAL 90 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 91 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 92 93 /* select serial console configuration */ 94 #define CONFIG_CONS_INDEX 3 95 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 96 #define CONFIG_SERIAL3 3 97 #define CONFIG_BAUDRATE 115200 98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 99 115200} 100 101 /* MMC */ 102 #define CONFIG_GENERIC_MMC 103 #define CONFIG_MMC 104 #define CONFIG_OMAP_HSMMC 105 #define CONFIG_DOS_PARTITION 106 107 /* I2C */ 108 #define CONFIG_SYS_I2C 109 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 110 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 111 #define CONFIG_SYS_I2C_OMAP34XX 112 113 114 /* EEPROM */ 115 #define CONFIG_CMD_EEPROM 116 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 117 #define CONFIG_SYS_EEPROM_BUS_NUM 1 118 119 /* TWL4030 */ 120 #define CONFIG_TWL4030_POWER 121 #define CONFIG_TWL4030_LED 122 123 /* Board NAND Info */ 124 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 125 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 126 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 127 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 128 "128k(SPL)," \ 129 "1m(u-boot)," \ 130 "384k(u-boot-env1)," \ 131 "1152k(mtdoops)," \ 132 "384k(u-boot-env2)," \ 133 "5m(kernel)," \ 134 "2m(fdt)," \ 135 "-(ubi)" 136 137 #define CONFIG_NAND_OMAP_GPMC 138 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 139 /* to access nand */ 140 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 141 /* to access nand at */ 142 /* CS0 */ 143 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 144 /* devices */ 145 #define CONFIG_BCH 146 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 147 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 148 149 /* commands to include */ 150 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 151 #define CONFIG_CMD_FAT /* FAT support */ 152 #define CONFIG_CMD_I2C /* I2C serial bus support */ 153 #define CONFIG_CMD_MMC /* MMC support */ 154 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 155 #define CONFIG_CMD_NAND /* NAND support */ 156 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 157 #define CONFIG_CMD_UBI /* UBI commands */ 158 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 159 #define CONFIG_LZO /* LZO is needed for UBIFS */ 160 161 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 162 163 /* needed for ubi */ 164 #define CONFIG_RBTREE 165 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 166 #define CONFIG_MTD_PARTITIONS 167 168 /* Environment information (this is the common part) */ 169 170 #define CONFIG_BOOTDELAY 0 171 172 /* hang() the board on panic() */ 173 #define CONFIG_PANIC_HANG 174 175 /* environment placement (for NAND), is different for FLASHCARD but does not 176 * harm there */ 177 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 178 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 179 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 180 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 181 182 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 183 * value can not be used here! */ 184 #define CONFIG_LOADADDR 0x82000000 185 186 #define CONFIG_COMMON_ENV_SETTINGS \ 187 "console=ttyO2,115200n8\0" \ 188 "mmcdev=0\0" \ 189 "vram=3M\0" \ 190 "defaultdisplay=lcd\0" \ 191 "kernelopts=mtdoops.mtddev=3\0" \ 192 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 193 "mtdids=" MTDIDS_DEFAULT "\0" \ 194 "commonargs=" \ 195 "setenv bootargs console=${console} " \ 196 "${mtdparts} " \ 197 "${kernelopts} " \ 198 "vt.global_cursor_default=0 " \ 199 "vram=${vram} " \ 200 "omapdss.def_disp=${defaultdisplay}\0" 201 202 #define CONFIG_BOOTCOMMAND "run autoboot" 203 204 /* specific environment settings for different use cases 205 * FLASHCARD: used to run a rdimage from sdcard to program the device 206 * 'NORMAL': used to boot kernel from sdcard, nand, ... 207 * 208 * The main aim for the FLASHCARD skin is to have an embedded environment 209 * which will not be influenced by any data already on the device. 210 */ 211 #ifdef CONFIG_FLASHCARD 212 213 #define CONFIG_ENV_IS_NOWHERE 214 215 /* the rdaddr is 16 MiB before the loadaddr */ 216 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 217 218 #define CONFIG_EXTRA_ENV_SETTINGS \ 219 CONFIG_COMMON_ENV_SETTINGS \ 220 CONFIG_ENV_RDADDR \ 221 "autoboot=" \ 222 "run commonargs; " \ 223 "setenv bootargs ${bootargs} " \ 224 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 225 "rdinit=/sbin/init; " \ 226 "mmc dev ${mmcdev}; mmc rescan; " \ 227 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 228 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 229 "bootm ${loadaddr} ${rdaddr}\0" 230 231 #else /* CONFIG_FLASHCARD */ 232 233 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 234 235 #define CONFIG_ENV_IS_IN_NAND 236 237 #define CONFIG_EXTRA_ENV_SETTINGS \ 238 CONFIG_COMMON_ENV_SETTINGS \ 239 "mmcargs=" \ 240 "run commonargs; " \ 241 "setenv bootargs ${bootargs} " \ 242 "root=/dev/mmcblk0p2 " \ 243 "rootwait " \ 244 "rw\0" \ 245 "nandargs=" \ 246 "run commonargs; " \ 247 "setenv bootargs ${bootargs} " \ 248 "root=ubi0:root " \ 249 "ubi.mtd=7 " \ 250 "rootfstype=ubifs " \ 251 "ro\0" \ 252 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 253 "bootscript=echo Running bootscript from mmc ...; " \ 254 "source ${loadaddr}\0" \ 255 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 256 "mmcboot=echo Booting from mmc ...; " \ 257 "run mmcargs; " \ 258 "bootm ${loadaddr}\0" \ 259 "loaduimage_ubi=ubi part ubi; " \ 260 "ubifsmount ubi:root; " \ 261 "ubifsload ${loadaddr} /boot/uImage\0" \ 262 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 263 "nandboot=echo Booting from nand ...; " \ 264 "run nandargs; " \ 265 "run loaduimage_nand; " \ 266 "bootm ${loadaddr}\0" \ 267 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 268 "if run loadbootscript; then " \ 269 "run bootscript; " \ 270 "else " \ 271 "if run loaduimage; then " \ 272 "run mmcboot; " \ 273 "else run nandboot; " \ 274 "fi; " \ 275 "fi; " \ 276 "else run nandboot; fi\0" 277 278 #endif /* CONFIG_FLASHCARD */ 279 280 /* Miscellaneous configurable options */ 281 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 282 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 283 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 284 #define CONFIG_AUTO_COMPLETE 285 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 286 /* Print Buffer Size */ 287 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 288 sizeof(CONFIG_SYS_PROMPT) + 16) 289 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 290 291 /* Boot Argument Buffer Size */ 292 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 293 294 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 295 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 296 0x07000000) /* 112 MB */ 297 298 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 299 300 /* 301 * OMAP3 has 12 GP timers, they can be driven by the system clock 302 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 303 * This rate is divided by a local divisor. 304 */ 305 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 306 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 307 308 /* Physical Memory Map */ 309 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 310 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 311 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 312 313 /* NAND and environment organization */ 314 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 315 316 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 317 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 318 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 319 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 320 CONFIG_SYS_INIT_RAM_SIZE - \ 321 GENERATED_GBL_DATA_SIZE) 322 323 /* SRAM config */ 324 #define CONFIG_SYS_SRAM_START 0x40200000 325 #define CONFIG_SYS_SRAM_SIZE 0x10000 326 327 /* Defines for SPL */ 328 #define CONFIG_SPL_FRAMEWORK 329 #define CONFIG_SPL_NAND_SIMPLE 330 331 #define CONFIG_SPL_BOARD_INIT 332 #define CONFIG_SPL_GPIO_SUPPORT 333 #define CONFIG_SPL_LIBCOMMON_SUPPORT 334 #define CONFIG_SPL_LIBDISK_SUPPORT 335 #define CONFIG_SPL_I2C_SUPPORT 336 #define CONFIG_SPL_LIBGENERIC_SUPPORT 337 #define CONFIG_SPL_SERIAL_SUPPORT 338 #define CONFIG_SPL_POWER_SUPPORT 339 #define CONFIG_SPL_NAND_SUPPORT 340 #define CONFIG_SPL_NAND_BASE 341 #define CONFIG_SPL_NAND_DRIVERS 342 #define CONFIG_SPL_NAND_ECC 343 #define CONFIG_SPL_MMC_SUPPORT 344 #define CONFIG_SPL_FAT_SUPPORT 345 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 346 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 347 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 348 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 349 350 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 351 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ 352 353 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 354 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 355 356 /* NAND boot config */ 357 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 358 #define CONFIG_SYS_NAND_PAGE_COUNT 64 359 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 360 #define CONFIG_SYS_NAND_OOBSIZE 64 361 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 362 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 363 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 364 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 365 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 366 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 367 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 368 52, 53, 54, 55, 56} 369 370 #define CONFIG_SYS_NAND_ECCSIZE 512 371 #define CONFIG_SYS_NAND_ECCBYTES 13 372 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 373 374 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 375 376 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 377 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 378 379 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 380 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 381 382 #define CONFIG_SYS_ALT_MEMTEST 383 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 384 #endif /* __CONFIG_H */ 385