1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2012 8 * Corscience GmbH & Co. KG 9 * Thomas Weber <weber@corscience.de> 10 * 11 * Configuration settings for the Tricorder board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_THUMB_BUILD 21 #define CONFIG_OMAP /* in a TI OMAP core */ 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 28 /* 29 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 30 * 64 bytes before this address should be set aside for u-boot.img's 31 * header. That is 0x800FFFC0--0x80100000 should not be used for any 32 * other needs. 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0x80100000 35 36 #define CONFIG_SDRC /* The chip has SDRC controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap.h> 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 48 #define CONFIG_SETUP_MEMORY_TAGS 49 #define CONFIG_INITRD_TAG 50 #define CONFIG_REVISION_TAG 51 52 /* Size of malloc() pool */ 53 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 54 55 /* Hardware drivers */ 56 57 /* GPIO support */ 58 #define CONFIG_OMAP_GPIO 59 60 /* GPIO banks */ 61 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 62 63 /* LED support */ 64 #define CONFIG_STATUS_LED 65 #define CONFIG_BOARD_SPECIFIC_LED 66 #define CONFIG_CMD_LED /* LED command */ 67 #define STATUS_LED_BIT (1 << 0) 68 #define STATUS_LED_STATE STATUS_LED_ON 69 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 70 #define STATUS_LED_BIT1 (1 << 1) 71 #define STATUS_LED_STATE1 STATUS_LED_ON 72 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 73 #define STATUS_LED_BIT2 (1 << 2) 74 #define STATUS_LED_STATE2 STATUS_LED_ON 75 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 76 77 /* NS16550 Configuration */ 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 81 82 /* select serial console configuration */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 88 115200} 89 90 /* MMC */ 91 #define CONFIG_GENERIC_MMC 92 #define CONFIG_MMC 93 #define CONFIG_OMAP_HSMMC 94 #define CONFIG_DOS_PARTITION 95 96 /* I2C */ 97 #define CONFIG_SYS_I2C 98 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 99 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 100 #define CONFIG_SYS_I2C_OMAP34XX 101 102 103 /* EEPROM */ 104 #define CONFIG_CMD_EEPROM 105 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 106 #define CONFIG_SYS_EEPROM_BUS_NUM 1 107 108 /* TWL4030 */ 109 #define CONFIG_TWL4030_POWER 110 #define CONFIG_TWL4030_LED 111 112 /* Board NAND Info */ 113 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 114 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 115 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 116 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 117 "128k(SPL)," \ 118 "1m(u-boot)," \ 119 "384k(u-boot-env1)," \ 120 "1152k(mtdoops)," \ 121 "384k(u-boot-env2)," \ 122 "5m(kernel)," \ 123 "2m(fdt)," \ 124 "-(ubi)" 125 126 #define CONFIG_NAND_OMAP_GPMC 127 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 128 /* to access nand */ 129 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 130 /* to access nand at */ 131 /* CS0 */ 132 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 133 /* devices */ 134 #define CONFIG_BCH 135 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 136 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 137 138 /* commands to include */ 139 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 140 #define CONFIG_CMD_NAND /* NAND support */ 141 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 142 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 143 #define CONFIG_LZO /* LZO is needed for UBIFS */ 144 145 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 146 147 /* needed for ubi */ 148 #define CONFIG_RBTREE 149 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 150 #define CONFIG_MTD_PARTITIONS 151 152 /* Environment information (this is the common part) */ 153 154 155 /* hang() the board on panic() */ 156 #define CONFIG_PANIC_HANG 157 158 /* environment placement (for NAND), is different for FLASHCARD but does not 159 * harm there */ 160 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 161 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 162 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 163 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 164 165 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 166 * value can not be used here! */ 167 #define CONFIG_LOADADDR 0x82000000 168 169 #define CONFIG_COMMON_ENV_SETTINGS \ 170 "console=ttyO2,115200n8\0" \ 171 "mmcdev=0\0" \ 172 "vram=3M\0" \ 173 "defaultdisplay=lcd\0" \ 174 "kernelopts=mtdoops.mtddev=3\0" \ 175 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 176 "mtdids=" MTDIDS_DEFAULT "\0" \ 177 "commonargs=" \ 178 "setenv bootargs console=${console} " \ 179 "${mtdparts} " \ 180 "${kernelopts} " \ 181 "vt.global_cursor_default=0 " \ 182 "vram=${vram} " \ 183 "omapdss.def_disp=${defaultdisplay}\0" 184 185 #define CONFIG_BOOTCOMMAND "run autoboot" 186 187 /* specific environment settings for different use cases 188 * FLASHCARD: used to run a rdimage from sdcard to program the device 189 * 'NORMAL': used to boot kernel from sdcard, nand, ... 190 * 191 * The main aim for the FLASHCARD skin is to have an embedded environment 192 * which will not be influenced by any data already on the device. 193 */ 194 #ifdef CONFIG_FLASHCARD 195 196 #define CONFIG_ENV_IS_NOWHERE 197 198 /* the rdaddr is 16 MiB before the loadaddr */ 199 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 200 201 #define CONFIG_EXTRA_ENV_SETTINGS \ 202 CONFIG_COMMON_ENV_SETTINGS \ 203 CONFIG_ENV_RDADDR \ 204 "autoboot=" \ 205 "run commonargs; " \ 206 "setenv bootargs ${bootargs} " \ 207 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 208 "rdinit=/sbin/init; " \ 209 "mmc dev ${mmcdev}; mmc rescan; " \ 210 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 211 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 212 "bootm ${loadaddr} ${rdaddr}\0" 213 214 #else /* CONFIG_FLASHCARD */ 215 216 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 217 218 #define CONFIG_ENV_IS_IN_NAND 219 220 #define CONFIG_EXTRA_ENV_SETTINGS \ 221 CONFIG_COMMON_ENV_SETTINGS \ 222 "mmcargs=" \ 223 "run commonargs; " \ 224 "setenv bootargs ${bootargs} " \ 225 "root=/dev/mmcblk0p2 " \ 226 "rootwait " \ 227 "rw\0" \ 228 "nandargs=" \ 229 "run commonargs; " \ 230 "setenv bootargs ${bootargs} " \ 231 "root=ubi0:root " \ 232 "ubi.mtd=7 " \ 233 "rootfstype=ubifs " \ 234 "ro\0" \ 235 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 236 "bootscript=echo Running bootscript from mmc ...; " \ 237 "source ${loadaddr}\0" \ 238 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 239 "mmcboot=echo Booting from mmc ...; " \ 240 "run mmcargs; " \ 241 "bootm ${loadaddr}\0" \ 242 "loaduimage_ubi=ubi part ubi; " \ 243 "ubifsmount ubi:root; " \ 244 "ubifsload ${loadaddr} /boot/uImage\0" \ 245 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 246 "nandboot=echo Booting from nand ...; " \ 247 "run nandargs; " \ 248 "run loaduimage_nand; " \ 249 "bootm ${loadaddr}\0" \ 250 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 251 "if run loadbootscript; then " \ 252 "run bootscript; " \ 253 "else " \ 254 "if run loaduimage; then " \ 255 "run mmcboot; " \ 256 "else run nandboot; " \ 257 "fi; " \ 258 "fi; " \ 259 "else run nandboot; fi\0" 260 261 #endif /* CONFIG_FLASHCARD */ 262 263 /* Miscellaneous configurable options */ 264 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 265 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 266 #define CONFIG_AUTO_COMPLETE 267 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 268 /* Print Buffer Size */ 269 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 270 sizeof(CONFIG_SYS_PROMPT) + 16) 271 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 272 273 /* Boot Argument Buffer Size */ 274 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 275 276 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 277 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 278 0x07000000) /* 112 MB */ 279 280 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 281 282 /* 283 * OMAP3 has 12 GP timers, they can be driven by the system clock 284 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 285 * This rate is divided by a local divisor. 286 */ 287 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 288 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 289 290 /* Physical Memory Map */ 291 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 292 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 293 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 294 295 /* NAND and environment organization */ 296 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 297 298 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 299 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 300 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 301 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 302 CONFIG_SYS_INIT_RAM_SIZE - \ 303 GENERATED_GBL_DATA_SIZE) 304 305 /* SRAM config */ 306 #define CONFIG_SYS_SRAM_START 0x40200000 307 #define CONFIG_SYS_SRAM_SIZE 0x10000 308 309 /* Defines for SPL */ 310 #define CONFIG_SPL_FRAMEWORK 311 #define CONFIG_SPL_NAND_SIMPLE 312 313 #define CONFIG_SPL_BOARD_INIT 314 #define CONFIG_SPL_NAND_BASE 315 #define CONFIG_SPL_NAND_DRIVERS 316 #define CONFIG_SPL_NAND_ECC 317 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 318 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 319 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 320 321 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 322 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 323 CONFIG_SPL_TEXT_BASE) 324 325 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 326 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 327 328 /* NAND boot config */ 329 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 330 #define CONFIG_SYS_NAND_PAGE_COUNT 64 331 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 332 #define CONFIG_SYS_NAND_OOBSIZE 64 333 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 334 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 335 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 336 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 337 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 338 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 339 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 340 52, 53, 54, 55, 56} 341 342 #define CONFIG_SYS_NAND_ECCSIZE 512 343 #define CONFIG_SYS_NAND_ECCBYTES 13 344 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 345 346 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 347 348 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 349 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 350 351 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 352 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 353 354 #define CONFIG_SYS_ALT_MEMTEST 355 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 356 #endif /* __CONFIG_H */ 357