xref: /openbmc/u-boot/include/configs/trats2.h (revision 7ffce4f1)
1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  * Sanghee Kim <sh0130.kim@samsung.com>
4  * Piotr Wilczek <p.wilczek@samsung.com>
5  *
6  * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __CONFIG_TRATS2_H
12 #define __CONFIG_TRATS2_H
13 
14 #include <configs/exynos4-common.h>
15 
16 #define CONFIG_TIZEN			/* TIZEN lib */
17 
18 #define CONFIG_SYS_L2CACHE_OFF
19 #ifndef CONFIG_SYS_L2CACHE_OFF
20 #define CONFIG_SYS_L2_PL310
21 #define CONFIG_SYS_PL310_BASE	0x10502000
22 #endif
23 
24 /* TRATS2 has 4 banks of DRAM */
25 #define CONFIG_NR_DRAM_BANKS		4
26 #define CONFIG_SYS_SDRAM_BASE		0x40000000
27 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
28 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
29 /* memtest works on */
30 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
31 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
32 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
33 
34 #define CONFIG_SYS_TEXT_BASE		0x43e00000
35 
36 /* select serial console configuration */
37 #define CONFIG_SERIAL2
38 
39 /* Console configuration */
40 
41 #define CONFIG_BOOTARGS			"Please use defined boot"
42 #define CONFIG_BOOTCOMMAND		"run autoboot"
43 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
44 
45 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
46 					- GENERATED_GBL_DATA_SIZE)
47 
48 #define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
49 
50 #define CONFIG_SYS_MONITOR_BASE	0x00000000
51 
52 #define CONFIG_ENV_IS_IN_MMC
53 #define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
54 #define CONFIG_ENV_SIZE			4096
55 #define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
56 
57 #define CONFIG_ENV_OVERWRITE
58 
59 #define CONFIG_ENV_VARS_UBOOT_CONFIG
60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
61 
62 /* Tizen - partitions definitions */
63 #define PARTS_CSA		"csa-mmc"
64 #define PARTS_BOOT		"boot"
65 #define PARTS_QBOOT		"qboot"
66 #define PARTS_CSC		"csc"
67 #define PARTS_ROOT		"platform"
68 #define PARTS_DATA		"data"
69 #define PARTS_UMS		"ums"
70 
71 #define PARTS_DEFAULT \
72 	"uuid_disk=${uuid_gpt_disk};" \
73 	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
74 	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
75 	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
76 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
77 	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
78 	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
79 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
80 
81 #define CONFIG_DFU_ALT \
82 	"u-boot raw 0x80 0x800;" \
83 	"/uImage ext4 0 2;" \
84 	"/modem.bin ext4 0 2;" \
85 	"/exynos4412-trats2.dtb ext4 0 2;" \
86 	""PARTS_CSA" part 0 1;" \
87 	""PARTS_BOOT" part 0 2;" \
88 	""PARTS_QBOOT" part 0 3;" \
89 	""PARTS_CSC" part 0 4;" \
90 	""PARTS_ROOT" part 0 5;" \
91 	""PARTS_DATA" part 0 6;" \
92 	""PARTS_UMS" part 0 7;" \
93 	"params.bin raw 0x38 0x8;" \
94 	"/Image.itb ext4 0 2\0"
95 
96 #define CONFIG_EXTRA_ENV_SETTINGS \
97 	"bootk=" \
98 		"run loaduimage;" \
99 		"if run loaddtb; then " \
100 			"bootm 0x40007FC0 - ${fdtaddr};" \
101 		"fi;" \
102 		"bootm 0x40007FC0;\0" \
103 	"updatebackup=" \
104 		"mmc dev 0 2; mmc write 0x51000000 0 0x800;" \
105 		" mmc dev 0 0\0" \
106 	"updatebootb=" \
107 		"mmc read 0x51000000 0x80 0x800; run updatebackup\0" \
108 	"mmcboot=" \
109 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
110 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
111 		"run bootk\0" \
112 	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
113 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
114 	"verify=n\0" \
115 	"rootfstype=ext4\0" \
116 	"console=" CONFIG_DEFAULT_CONSOLE \
117 	"kernelname=uImage\0" \
118 	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
119 		"${kernelname}\0" \
120 	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
121 		"${fdtfile}\0" \
122 	"mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
123 	"mmcbootpart=2\0" \
124 	"mmcrootpart=5\0" \
125 	"opts=always_resume=1\0" \
126 	"partitions=" PARTS_DEFAULT \
127 	"dfu_alt_info=" CONFIG_DFU_ALT \
128 	"uartpath=ap\0" \
129 	"usbpath=ap\0" \
130 	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
131 	"consoleoff=set console console=ram; save; reset\0" \
132 	"spladdr=0x40000100\0" \
133 	"splsize=0x200\0" \
134 	"splfile=falcon.bin\0" \
135 	"spl_export=" \
136 		   "setexpr spl_imgsize ${splsize} + 8 ;" \
137 		   "setenv spl_imgsize 0x${spl_imgsize};" \
138 		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
139 		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
140 		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
141 		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
142 		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
143 		   "spl export atags 0x40007FC0;" \
144 		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
145 		   "mw.l ${spl_addr_tmp} ${splsize};" \
146 		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
147 		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
148 		   "setenv spl_imgsize;" \
149 		   "setenv spl_imgaddr;" \
150 		   "setenv spl_addr_tmp;\0" \
151 	CONFIG_EXTRA_ENV_ITB \
152 	"fdtaddr=40800000\0" \
153 
154 /* GPT */
155 #define CONFIG_RANDOM_UUID
156 
157 /* Security subsystem - enable hw_rand() */
158 #define CONFIG_EXYNOS_ACE_SHA
159 #define CONFIG_LIB_HW_RAND
160 
161 /* Common misc for Samsung */
162 #define CONFIG_MISC_COMMON
163 
164 #define CONFIG_MISC_INIT_R
165 
166 /* Download menu - Samsung common */
167 #define CONFIG_LCD_MENU
168 #define CONFIG_LCD_MENU_BOARD
169 
170 /* Download menu - definitions for check keys */
171 #ifndef __ASSEMBLY__
172 #include <power/max77686_pmic.h>
173 
174 #define KEY_PWR_PMIC_NAME		"MAX77686_PMIC"
175 #define KEY_PWR_STATUS_REG		MAX77686_REG_PMIC_STATUS1
176 #define KEY_PWR_STATUS_MASK		(1 << 0)
177 #define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
178 #define KEY_PWR_INTERRUPT_MASK		(1 << 1)
179 
180 #define KEY_VOL_UP_GPIO			EXYNOS4X12_GPIO_X22
181 #define KEY_VOL_DOWN_GPIO		EXYNOS4X12_GPIO_X33
182 #endif /* __ASSEMBLY__ */
183 
184 /* LCD console */
185 #define LCD_BPP                 LCD_COLOR16
186 
187 /* LCD */
188 #define CONFIG_BMP_16BPP
189 #define CONFIG_FB_ADDR		0x52504000
190 #define CONFIG_EXYNOS_MIPI_DSIM
191 #define CONFIG_VIDEO_BMP_GZIP
192 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
193 
194 #endif	/* __CONFIG_H */
195