xref: /openbmc/u-boot/include/configs/trats.h (revision d9b23e26)
1 /*
2  * Copyright (C) 2011 Samsung Electronics
3  * Heungjun Kim <riverful.kim@samsung.com>
4  *
5  * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_TRATS_H
11 #define __CONFIG_TRATS_H
12 
13 #include <configs/exynos4-common.h>
14 
15 #define CONFIG_TRATS
16 
17 #define CONFIG_TIZEN			/* TIZEN lib */
18 
19 #define CONFIG_SYS_L2CACHE_OFF
20 #ifndef CONFIG_SYS_L2CACHE_OFF
21 #define CONFIG_SYS_L2_PL310
22 #define CONFIG_SYS_PL310_BASE	0x10502000
23 #endif
24 
25 /* TRATS has 4 banks of DRAM */
26 #define CONFIG_NR_DRAM_BANKS		4
27 #define CONFIG_SYS_SDRAM_BASE		0x40000000
28 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
29 #define CONFIG_SYS_TEXT_BASE		0x63300000
30 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
31 
32 /* memtest works on */
33 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
34 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
35 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
36 
37 #define CONFIG_SYS_TEXT_BASE		0x63300000
38 
39 /* select serial console configuration */
40 #define CONFIG_SERIAL2
41 
42 #define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
43 
44 #define CONFIG_BOOTCOMMAND		"run autoboot"
45 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
46 
47 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
48 					- GENERATED_GBL_DATA_SIZE)
49 
50 #define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
51 
52 #define CONFIG_SYS_MONITOR_BASE	0x00000000
53 
54 #define CONFIG_BOOTBLOCK		"10"
55 #define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
56 
57 #define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
58 #define CONFIG_ENV_SIZE			4096
59 #define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
60 
61 #define CONFIG_ENV_OVERWRITE
62 
63 #define CONFIG_ENV_VARS_UBOOT_CONFIG
64 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
65 
66 /* Tizen - partitions definitions */
67 #define PARTS_CSA		"csa-mmc"
68 #define PARTS_BOOT		"boot"
69 #define PARTS_QBOOT		"qboot"
70 #define PARTS_CSC		"csc"
71 #define PARTS_ROOT		"platform"
72 #define PARTS_DATA		"data"
73 #define PARTS_UMS		"ums"
74 
75 #define PARTS_DEFAULT \
76 	"uuid_disk=${uuid_gpt_disk};" \
77 	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
78 	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
79 	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
80 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
81 	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
82 	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
83 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
84 
85 #define CONFIG_DFU_ALT \
86 	"u-boot raw 0x80 0x400;" \
87 	"/uImage ext4 0 2;" \
88 	"/modem.bin ext4 0 2;" \
89 	"/exynos4210-trats.dtb ext4 0 2;" \
90 	""PARTS_CSA" part 0 1;" \
91 	""PARTS_BOOT" part 0 2;" \
92 	""PARTS_QBOOT" part 0 3;" \
93 	""PARTS_CSC" part 0 4;" \
94 	""PARTS_ROOT" part 0 5;" \
95 	""PARTS_DATA" part 0 6;" \
96 	""PARTS_UMS" part 0 7;" \
97 	"params.bin raw 0x38 0x8;" \
98 	"/Image.itb ext4 0 2\0"
99 
100 #define CONFIG_EXTRA_ENV_SETTINGS \
101 	"bootk=" \
102 		"run loaduimage;" \
103 		"if run loaddtb; then " \
104 			"bootm 0x40007FC0 - ${fdtaddr};" \
105 		"fi;" \
106 		"bootm 0x40007FC0;\0" \
107 	"updatebackup=" \
108 		"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
109 		"mmc dev 0 0\0" \
110 	"updatebootb=" \
111 		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
112 	"lpj=lpj=3981312\0" \
113 	"nfsboot=" \
114 		"setenv bootargs root=/dev/nfs rw " \
115 		"nfsroot=${nfsroot},nolock,tcp " \
116 		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
117 		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
118 		"; run bootk\0" \
119 	"ramfsboot=" \
120 		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
121 		"${console} ${meminfo} " \
122 		"initrd=0x43000000,8M ramdisk=8192\0" \
123 	"mmcboot=" \
124 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
125 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
126 		"run bootk\0" \
127 	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
128 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
129 	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
130 	"verify=n\0" \
131 	"rootfstype=ext4\0" \
132 	"console=" CONFIG_DEFAULT_CONSOLE \
133 	"meminfo=crashkernel=32M@0x50000000\0" \
134 	"nfsroot=/nfsroot/arm\0" \
135 	"bootblock=" CONFIG_BOOTBLOCK "\0" \
136 	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
137 	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
138 		"${fdtfile}\0" \
139 	"mmcdev=0\0" \
140 	"mmcbootpart=2\0" \
141 	"mmcrootpart=5\0" \
142 	"opts=always_resume=1\0" \
143 	"partitions=" PARTS_DEFAULT \
144 	"dfu_alt_info=" CONFIG_DFU_ALT \
145 	"spladdr=0x40000100\0" \
146 	"splsize=0x200\0" \
147 	"splfile=falcon.bin\0" \
148 	"spl_export=" \
149 		   "setexpr spl_imgsize ${splsize} + 8 ;" \
150 		   "setenv spl_imgsize 0x${spl_imgsize};" \
151 		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
152 		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
153 		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
154 		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
155 		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
156 		   "spl export atags 0x40007FC0;" \
157 		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
158 		   "mw.l ${spl_addr_tmp} ${splsize};" \
159 		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
160 		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
161 		   "setenv spl_imgsize;" \
162 		   "setenv spl_imgaddr;" \
163 		   "setenv spl_addr_tmp;\0" \
164 	CONFIG_EXTRA_ENV_ITB \
165 	"fdtaddr=40800000\0" \
166 
167 /* Falcon mode definitions */
168 #define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
169 
170 /* GPT */
171 #define CONFIG_RANDOM_UUID
172 
173 /* Security subsystem - enable hw_rand() */
174 #define CONFIG_EXYNOS_ACE_SHA
175 #define CONFIG_LIB_HW_RAND
176 
177 /* Common misc for Samsung */
178 #define CONFIG_MISC_COMMON
179 
180 #define CONFIG_MISC_INIT_R
181 
182 /* Download menu - Samsung common */
183 #define CONFIG_LCD_MENU
184 #define CONFIG_LCD_MENU_BOARD
185 
186 /* Download menu - definitions for check keys */
187 #ifndef __ASSEMBLY__
188 
189 #define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
190 #define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
191 #define KEY_PWR_STATUS_MASK		(1 << 0)
192 #define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
193 #define KEY_PWR_INTERRUPT_MASK		(1 << 0)
194 
195 #define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
196 #define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
197 #endif /* __ASSEMBLY__ */
198 
199 /* LCD console */
200 #define LCD_BPP			LCD_COLOR16
201 
202 /* LCD */
203 #define CONFIG_BMP_16BPP
204 #define CONFIG_FB_ADDR		0x52504000
205 #define CONFIG_EXYNOS_MIPI_DSIM
206 #define CONFIG_VIDEO_BMP_GZIP
207 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
208 
209 #endif	/* __CONFIG_H */
210