1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * 5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_TRATS_H 11 #define __CONFIG_TRATS_H 12 13 #include <configs/exynos4-dt.h> 14 15 #define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ 16 17 #define CONFIG_TRATS 18 19 #undef CONFIG_DEFAULT_DEVICE_TREE 20 #define CONFIG_DEFAULT_DEVICE_TREE exynos4210-trats 21 22 #define CONFIG_TIZEN /* TIZEN lib */ 23 24 #define CONFIG_SYS_L2CACHE_OFF 25 #ifndef CONFIG_SYS_L2CACHE_OFF 26 #define CONFIG_SYS_L2_PL310 27 #define CONFIG_SYS_PL310_BASE 0x10502000 28 #endif 29 30 /* TRATS has 4 banks of DRAM */ 31 #define CONFIG_NR_DRAM_BANKS 4 32 #define CONFIG_SYS_SDRAM_BASE 0x40000000 33 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 34 #define CONFIG_SYS_TEXT_BASE 0x63300000 35 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 36 37 /* memtest works on */ 38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 39 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) 40 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) 41 42 #define CONFIG_SYS_TEXT_BASE 0x63300000 43 44 #include <linux/sizes.h> 45 /* Size of malloc() pool */ 46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) 47 48 /* select serial console configuration */ 49 #define CONFIG_SERIAL2 50 #define CONFIG_BAUDRATE 115200 51 52 /* Console configuration */ 53 #define CONFIG_SYS_CONSOLE_INFO_QUIET 54 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 55 56 /* MACH_TYPE_TRATS macro will be removed once added to mach-types */ 57 #define MACH_TYPE_TRATS 3928 58 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS 59 60 #define CONFIG_BOOTARGS "Please use defined boot" 61 #define CONFIG_BOOTCOMMAND "run mmcboot" 62 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 63 64 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 65 - GENERATED_GBL_DATA_SIZE) 66 67 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 68 69 #define CONFIG_SYS_MONITOR_BASE 0x00000000 70 71 #define CONFIG_BOOTBLOCK "10" 72 #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" 73 74 #define CONFIG_ENV_IS_IN_MMC 75 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV 76 #define CONFIG_ENV_SIZE 4096 77 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ 78 79 #define CONFIG_ENV_OVERWRITE 80 81 #define CONFIG_ENV_VARS_UBOOT_CONFIG 82 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 83 84 /* Tizen - partitions definitions */ 85 #define PARTS_CSA "csa-mmc" 86 #define PARTS_BOOT "boot" 87 #define PARTS_QBOOT "qboot" 88 #define PARTS_CSC "csc" 89 #define PARTS_ROOT "platform" 90 #define PARTS_DATA "data" 91 #define PARTS_UMS "ums" 92 93 #define PARTS_DEFAULT \ 94 "uuid_disk=${uuid_gpt_disk};" \ 95 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 96 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 97 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 98 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 99 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 100 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 101 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 102 103 #define CONFIG_DFU_ALT \ 104 "u-boot raw 0x80 0x400;" \ 105 "uImage ext4 0 2;" \ 106 "modem.bin ext4 0 2;" \ 107 "exynos4210-trats.dtb ext4 0 2;" \ 108 ""PARTS_CSA" part 0 1;" \ 109 ""PARTS_BOOT" part 0 2;" \ 110 ""PARTS_QBOOT" part 0 3;" \ 111 ""PARTS_CSC" part 0 4;" \ 112 ""PARTS_ROOT" part 0 5;" \ 113 ""PARTS_DATA" part 0 6;" \ 114 ""PARTS_UMS" part 0 7;" \ 115 "params.bin raw 0x38 0x8\0" 116 117 #define CONFIG_EXTRA_ENV_SETTINGS \ 118 "bootk=" \ 119 "run loaduimage;" \ 120 "if run loaddtb; then " \ 121 "bootm 0x40007FC0 - ${fdtaddr};" \ 122 "fi;" \ 123 "bootm 0x40007FC0;\0" \ 124 "updatebackup=" \ 125 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ 126 "mmc dev 0 0\0" \ 127 "updatebootb=" \ 128 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ 129 "lpj=lpj=3981312\0" \ 130 "nfsboot=" \ 131 "setenv bootargs root=/dev/nfs rw " \ 132 "nfsroot=${nfsroot},nolock,tcp " \ 133 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 134 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ 135 "; run bootk\0" \ 136 "ramfsboot=" \ 137 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ 138 "${console} ${meminfo} " \ 139 "initrd=0x43000000,8M ramdisk=8192\0" \ 140 "mmcboot=" \ 141 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 142 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 143 "run bootk\0" \ 144 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ 145 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 146 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 147 "verify=n\0" \ 148 "rootfstype=ext4\0" \ 149 "console=" CONFIG_DEFAULT_CONSOLE \ 150 "meminfo=crashkernel=32M@0x50000000\0" \ 151 "nfsroot=/nfsroot/arm\0" \ 152 "bootblock=" CONFIG_BOOTBLOCK "\0" \ 153 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ 154 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 155 "${fdtfile}\0" \ 156 "mmcdev=0\0" \ 157 "mmcbootpart=2\0" \ 158 "mmcrootpart=5\0" \ 159 "opts=always_resume=1\0" \ 160 "partitions=" PARTS_DEFAULT \ 161 "dfu_alt_info=" CONFIG_DFU_ALT \ 162 "spladdr=0x40000100\0" \ 163 "splsize=0x200\0" \ 164 "splfile=falcon.bin\0" \ 165 "spl_export=" \ 166 "setexpr spl_imgsize ${splsize} + 8 ;" \ 167 "setenv spl_imgsize 0x${spl_imgsize};" \ 168 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 169 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 170 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 171 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 172 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 173 "spl export atags 0x40007FC0;" \ 174 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 175 "mw.l ${spl_addr_tmp} ${splsize};" \ 176 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 177 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 178 "setenv spl_imgsize;" \ 179 "setenv spl_imgaddr;" \ 180 "setenv spl_addr_tmp;\0" \ 181 "fdtaddr=40800000\0" \ 182 183 /* Falcon mode definitions */ 184 #define CONFIG_CMD_SPL 185 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 186 187 /* GPT */ 188 #define CONFIG_RANDOM_UUID 189 190 /* I2C */ 191 #include <asm/arch/gpio.h> 192 193 #define CONFIG_CMD_I2C 194 195 #define CONFIG_SYS_I2C 196 #define CONFIG_SYS_I2C_S3C24X0 197 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 198 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE 199 #define CONFIG_MAX_I2C_NUM 8 200 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 201 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 202 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 203 #define CONFIG_SOFT_I2C_READ_REPEATED_START 204 #define CONFIG_SYS_I2C_INIT_BOARD 205 206 /* I2C FG */ 207 #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41 208 #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40 209 210 /* POWER */ 211 #define CONFIG_POWER 212 #define CONFIG_POWER_I2C 213 #define CONFIG_POWER_MAX8997 214 215 #define CONFIG_POWER_FG 216 #define CONFIG_POWER_FG_MAX17042 217 #define CONFIG_POWER_MUIC 218 #define CONFIG_POWER_MUIC_MAX8997 219 #define CONFIG_POWER_BATTERY 220 #define CONFIG_POWER_BATTERY_TRATS 221 222 /* Security subsystem - enable hw_rand() */ 223 #define CONFIG_EXYNOS_ACE_SHA 224 #define CONFIG_LIB_HW_RAND 225 226 /* Common misc for Samsung */ 227 #define CONFIG_MISC_COMMON 228 229 #define CONFIG_MISC_INIT_R 230 231 /* Download menu - Samsung common */ 232 #define CONFIG_LCD_MENU 233 #define CONFIG_LCD_MENU_BOARD 234 235 /* Download menu - definitions for check keys */ 236 #ifndef __ASSEMBLY__ 237 #include <power/max8997_pmic.h> 238 239 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" 240 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 241 #define KEY_PWR_STATUS_MASK (1 << 0) 242 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 243 #define KEY_PWR_INTERRUPT_MASK (1 << 0) 244 245 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 246 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 247 #endif /* __ASSEMBLY__ */ 248 249 /* LCD console */ 250 #define LCD_BPP LCD_COLOR16 251 #define CONFIG_SYS_WHITE_ON_BLACK 252 253 /* LCD */ 254 #define CONFIG_EXYNOS_FB 255 #define CONFIG_LCD 256 #define CONFIG_CMD_BMP 257 #define CONFIG_BMP_16BPP 258 #define CONFIG_FB_ADDR 0x52504000 259 #define CONFIG_S6E8AX0 260 #define CONFIG_EXYNOS_MIPI_DSIM 261 #define CONFIG_VIDEO_BMP_GZIP 262 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) 263 264 #define LCD_XRES 720 265 #define LCD_YRES 1280 266 267 #endif /* __CONFIG_H */ 268