1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * 5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_TRATS_H 11 #define __CONFIG_TRATS_H 12 13 #include <configs/exynos4-common.h> 14 15 #define CONFIG_TRATS 16 17 #define CONFIG_TIZEN /* TIZEN lib */ 18 19 #define CONFIG_SYS_L2CACHE_OFF 20 #ifndef CONFIG_SYS_L2CACHE_OFF 21 #define CONFIG_SYS_L2_PL310 22 #define CONFIG_SYS_PL310_BASE 0x10502000 23 #endif 24 25 /* TRATS has 4 banks of DRAM */ 26 #define CONFIG_NR_DRAM_BANKS 4 27 #define CONFIG_SYS_SDRAM_BASE 0x40000000 28 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 29 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 30 31 /* memtest works on */ 32 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) 34 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) 35 36 /* select serial console configuration */ 37 #define CONFIG_SERIAL2 38 39 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS 40 41 #define CONFIG_BOOTCOMMAND "run autoboot" 42 #define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 43 44 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 45 - GENERATED_GBL_DATA_SIZE) 46 47 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 48 49 #define CONFIG_SYS_MONITOR_BASE 0x00000000 50 51 #define CONFIG_BOOTBLOCK "10" 52 #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" 53 54 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV 55 #define CONFIG_ENV_SIZE 4096 56 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #define CONFIG_ENV_VARS_UBOOT_CONFIG 61 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 62 63 /* Tizen - partitions definitions */ 64 #define PARTS_CSA "csa-mmc" 65 #define PARTS_BOOT "boot" 66 #define PARTS_QBOOT "qboot" 67 #define PARTS_CSC "csc" 68 #define PARTS_ROOT "platform" 69 #define PARTS_DATA "data" 70 #define PARTS_UMS "ums" 71 72 #define PARTS_DEFAULT \ 73 "uuid_disk=${uuid_gpt_disk};" \ 74 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 75 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 76 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 77 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 78 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 79 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 80 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 81 82 #define CONFIG_DFU_ALT \ 83 "u-boot raw 0x80 0x400;" \ 84 "/uImage ext4 0 2;" \ 85 "/modem.bin ext4 0 2;" \ 86 "/exynos4210-trats.dtb ext4 0 2;" \ 87 ""PARTS_CSA" part 0 1;" \ 88 ""PARTS_BOOT" part 0 2;" \ 89 ""PARTS_QBOOT" part 0 3;" \ 90 ""PARTS_CSC" part 0 4;" \ 91 ""PARTS_ROOT" part 0 5;" \ 92 ""PARTS_DATA" part 0 6;" \ 93 ""PARTS_UMS" part 0 7;" \ 94 "params.bin raw 0x38 0x8;" \ 95 "/Image.itb ext4 0 2\0" 96 97 #define CONFIG_EXTRA_ENV_SETTINGS \ 98 "bootk=" \ 99 "run loaduimage;" \ 100 "if run loaddtb; then " \ 101 "bootm 0x40007FC0 - ${fdtaddr};" \ 102 "fi;" \ 103 "bootm 0x40007FC0;\0" \ 104 "updatebackup=" \ 105 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ 106 "mmc dev 0 0\0" \ 107 "updatebootb=" \ 108 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ 109 "lpj=lpj=3981312\0" \ 110 "nfsboot=" \ 111 "setenv bootargs root=/dev/nfs rw " \ 112 "nfsroot=${nfsroot},nolock,tcp " \ 113 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 114 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ 115 "; run bootk\0" \ 116 "ramfsboot=" \ 117 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ 118 "${console} ${meminfo} " \ 119 "initrd=0x43000000,8M ramdisk=8192\0" \ 120 "mmcboot=" \ 121 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 122 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 123 "run bootk\0" \ 124 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ 125 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 126 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 127 "verify=n\0" \ 128 "rootfstype=ext4\0" \ 129 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 130 "meminfo=crashkernel=32M@0x50000000\0" \ 131 "nfsroot=/nfsroot/arm\0" \ 132 "bootblock=" CONFIG_BOOTBLOCK "\0" \ 133 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ 134 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 135 "${fdtfile}\0" \ 136 "mmcdev=0\0" \ 137 "mmcbootpart=2\0" \ 138 "mmcrootpart=5\0" \ 139 "opts=always_resume=1\0" \ 140 "partitions=" PARTS_DEFAULT \ 141 "dfu_alt_info=" CONFIG_DFU_ALT \ 142 "spladdr=0x40000100\0" \ 143 "splsize=0x200\0" \ 144 "splfile=falcon.bin\0" \ 145 "spl_export=" \ 146 "setexpr spl_imgsize ${splsize} + 8 ;" \ 147 "setenv spl_imgsize 0x${spl_imgsize};" \ 148 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 149 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 150 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 151 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 152 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 153 "spl export atags 0x40007FC0;" \ 154 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 155 "mw.l ${spl_addr_tmp} ${splsize};" \ 156 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 157 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 158 "setenv spl_imgsize;" \ 159 "setenv spl_imgaddr;" \ 160 "setenv spl_addr_tmp;\0" \ 161 CONFIG_EXTRA_ENV_ITB \ 162 "fdtaddr=40800000\0" \ 163 164 /* Falcon mode definitions */ 165 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 166 167 /* GPT */ 168 169 /* Security subsystem - enable hw_rand() */ 170 #define CONFIG_EXYNOS_ACE_SHA 171 172 /* Common misc for Samsung */ 173 #define CONFIG_MISC_COMMON 174 175 #define CONFIG_MISC_INIT_R 176 177 /* Download menu - Samsung common */ 178 #define CONFIG_LCD_MENU 179 180 /* Download menu - definitions for check keys */ 181 #ifndef __ASSEMBLY__ 182 183 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" 184 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 185 #define KEY_PWR_STATUS_MASK (1 << 0) 186 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 187 #define KEY_PWR_INTERRUPT_MASK (1 << 0) 188 189 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 190 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 191 #endif /* __ASSEMBLY__ */ 192 193 /* LCD console */ 194 #define LCD_BPP LCD_COLOR16 195 196 /* LCD */ 197 #define CONFIG_BMP_16BPP 198 #define CONFIG_FB_ADDR 0x52504000 199 #define CONFIG_EXYNOS_MIPI_DSIM 200 #define CONFIG_VIDEO_BMP_GZIP 201 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) 202 203 #endif /* __CONFIG_H */ 204