1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * 5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_TRATS_H 11 #define __CONFIG_TRATS_H 12 13 #include <configs/exynos4-common.h> 14 15 #define CONFIG_TRATS 16 17 #define CONFIG_TIZEN /* TIZEN lib */ 18 19 #define CONFIG_SYS_L2CACHE_OFF 20 #ifndef CONFIG_SYS_L2CACHE_OFF 21 #define CONFIG_SYS_L2_PL310 22 #define CONFIG_SYS_PL310_BASE 0x10502000 23 #endif 24 25 /* TRATS has 4 banks of DRAM */ 26 #define CONFIG_NR_DRAM_BANKS 4 27 #define CONFIG_SYS_SDRAM_BASE 0x40000000 28 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 29 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 30 31 /* memtest works on */ 32 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) 34 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) 35 36 /* select serial console configuration */ 37 #define CONFIG_SERIAL2 38 39 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS 40 41 #define CONFIG_BOOTCOMMAND "run autoboot" 42 #define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 43 44 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 45 - GENERATED_GBL_DATA_SIZE) 46 47 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 48 49 #define CONFIG_SYS_MONITOR_BASE 0x00000000 50 51 #define CONFIG_BOOTBLOCK "10" 52 #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" 53 54 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV 55 #define CONFIG_ENV_SIZE 4096 56 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 61 62 /* Tizen - partitions definitions */ 63 #define PARTS_CSA "csa-mmc" 64 #define PARTS_BOOT "boot" 65 #define PARTS_QBOOT "qboot" 66 #define PARTS_CSC "csc" 67 #define PARTS_ROOT "platform" 68 #define PARTS_DATA "data" 69 #define PARTS_UMS "ums" 70 71 #define PARTS_DEFAULT \ 72 "uuid_disk=${uuid_gpt_disk};" \ 73 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 74 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 75 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 76 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 77 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 78 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 79 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 80 81 #define CONFIG_DFU_ALT \ 82 "u-boot raw 0x80 0x400;" \ 83 "/uImage ext4 0 2;" \ 84 "/modem.bin ext4 0 2;" \ 85 "/exynos4210-trats.dtb ext4 0 2;" \ 86 ""PARTS_CSA" part 0 1;" \ 87 ""PARTS_BOOT" part 0 2;" \ 88 ""PARTS_QBOOT" part 0 3;" \ 89 ""PARTS_CSC" part 0 4;" \ 90 ""PARTS_ROOT" part 0 5;" \ 91 ""PARTS_DATA" part 0 6;" \ 92 ""PARTS_UMS" part 0 7;" \ 93 "params.bin raw 0x38 0x8;" \ 94 "/Image.itb ext4 0 2\0" 95 96 #define CONFIG_EXTRA_ENV_SETTINGS \ 97 "bootk=" \ 98 "run loaduimage;" \ 99 "if run loaddtb; then " \ 100 "bootm 0x40007FC0 - ${fdtaddr};" \ 101 "fi;" \ 102 "bootm 0x40007FC0;\0" \ 103 "updatebackup=" \ 104 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ 105 "mmc dev 0 0\0" \ 106 "updatebootb=" \ 107 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ 108 "lpj=lpj=3981312\0" \ 109 "nfsboot=" \ 110 "setenv bootargs root=/dev/nfs rw " \ 111 "nfsroot=${nfsroot},nolock,tcp " \ 112 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 113 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ 114 "; run bootk\0" \ 115 "ramfsboot=" \ 116 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ 117 "${console} ${meminfo} " \ 118 "initrd=0x43000000,8M ramdisk=8192\0" \ 119 "mmcboot=" \ 120 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 121 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 122 "run bootk\0" \ 123 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ 124 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 125 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 126 "verify=n\0" \ 127 "rootfstype=ext4\0" \ 128 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 129 "meminfo=crashkernel=32M@0x50000000\0" \ 130 "nfsroot=/nfsroot/arm\0" \ 131 "bootblock=" CONFIG_BOOTBLOCK "\0" \ 132 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ 133 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 134 "${fdtfile}\0" \ 135 "mmcdev=0\0" \ 136 "mmcbootpart=2\0" \ 137 "mmcrootpart=5\0" \ 138 "opts=always_resume=1\0" \ 139 "partitions=" PARTS_DEFAULT \ 140 "dfu_alt_info=" CONFIG_DFU_ALT \ 141 "spladdr=0x40000100\0" \ 142 "splsize=0x200\0" \ 143 "splfile=falcon.bin\0" \ 144 "spl_export=" \ 145 "setexpr spl_imgsize ${splsize} + 8 ;" \ 146 "setenv spl_imgsize 0x${spl_imgsize};" \ 147 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 148 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 149 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 150 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 151 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 152 "spl export atags 0x40007FC0;" \ 153 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 154 "mw.l ${spl_addr_tmp} ${splsize};" \ 155 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 156 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 157 "setenv spl_imgsize;" \ 158 "setenv spl_imgaddr;" \ 159 "setenv spl_addr_tmp;\0" \ 160 CONFIG_EXTRA_ENV_ITB \ 161 "fdtaddr=40800000\0" \ 162 163 /* Falcon mode definitions */ 164 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 165 166 /* GPT */ 167 168 /* Security subsystem - enable hw_rand() */ 169 #define CONFIG_EXYNOS_ACE_SHA 170 171 /* Common misc for Samsung */ 172 #define CONFIG_MISC_COMMON 173 174 #define CONFIG_MISC_INIT_R 175 176 /* Download menu - Samsung common */ 177 #define CONFIG_LCD_MENU 178 179 /* Download menu - definitions for check keys */ 180 #ifndef __ASSEMBLY__ 181 182 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" 183 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 184 #define KEY_PWR_STATUS_MASK (1 << 0) 185 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 186 #define KEY_PWR_INTERRUPT_MASK (1 << 0) 187 188 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 189 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 190 #endif /* __ASSEMBLY__ */ 191 192 /* LCD console */ 193 #define LCD_BPP LCD_COLOR16 194 195 /* LCD */ 196 #define CONFIG_BMP_16BPP 197 #define CONFIG_FB_ADDR 0x52504000 198 #define CONFIG_EXYNOS_MIPI_DSIM 199 #define CONFIG_VIDEO_BMP_GZIP 200 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) 201 202 #endif /* __CONFIG_H */ 203