1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Samsung Electronics 4 * Heungjun Kim <riverful.kim@samsung.com> 5 * 6 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. 7 */ 8 9 #ifndef __CONFIG_TRATS_H 10 #define __CONFIG_TRATS_H 11 12 #include <configs/exynos4-common.h> 13 14 #define CONFIG_TRATS 15 16 #define CONFIG_TIZEN /* TIZEN lib */ 17 18 #define CONFIG_SYS_L2CACHE_OFF 19 #ifndef CONFIG_SYS_L2CACHE_OFF 20 #define CONFIG_SYS_L2_PL310 21 #define CONFIG_SYS_PL310_BASE 0x10502000 22 #endif 23 24 /* TRATS has 4 banks of DRAM */ 25 #define CONFIG_NR_DRAM_BANKS 4 26 #define CONFIG_SYS_SDRAM_BASE 0x40000000 27 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 28 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 29 30 /* memtest works on */ 31 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 32 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) 33 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) 34 35 /* select serial console configuration */ 36 #define CONFIG_SERIAL2 37 38 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS 39 40 #define CONFIG_BOOTCOMMAND "run autoboot" 41 #define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 42 43 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 44 - GENERATED_GBL_DATA_SIZE) 45 46 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 47 48 #define CONFIG_SYS_MONITOR_BASE 0x00000000 49 50 #define CONFIG_BOOTBLOCK "10" 51 #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" 52 53 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV 54 #define CONFIG_ENV_SIZE 4096 55 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ 56 57 #define CONFIG_ENV_OVERWRITE 58 59 /* Tizen - partitions definitions */ 60 #define PARTS_CSA "csa-mmc" 61 #define PARTS_BOOT "boot" 62 #define PARTS_QBOOT "qboot" 63 #define PARTS_CSC "csc" 64 #define PARTS_ROOT "platform" 65 #define PARTS_DATA "data" 66 #define PARTS_UMS "ums" 67 68 #define PARTS_DEFAULT \ 69 "uuid_disk=${uuid_gpt_disk};" \ 70 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 71 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 72 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 73 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 74 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 75 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 76 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 77 78 #define CONFIG_DFU_ALT \ 79 "u-boot raw 0x80 0x400;" \ 80 "/uImage ext4 0 2;" \ 81 "/modem.bin ext4 0 2;" \ 82 "/exynos4210-trats.dtb ext4 0 2;" \ 83 ""PARTS_CSA" part 0 1;" \ 84 ""PARTS_BOOT" part 0 2;" \ 85 ""PARTS_QBOOT" part 0 3;" \ 86 ""PARTS_CSC" part 0 4;" \ 87 ""PARTS_ROOT" part 0 5;" \ 88 ""PARTS_DATA" part 0 6;" \ 89 ""PARTS_UMS" part 0 7;" \ 90 "params.bin raw 0x38 0x8;" \ 91 "/Image.itb ext4 0 2\0" 92 93 #define CONFIG_EXTRA_ENV_SETTINGS \ 94 "bootk=" \ 95 "run loaduimage;" \ 96 "if run loaddtb; then " \ 97 "bootm 0x40007FC0 - ${fdtaddr};" \ 98 "fi;" \ 99 "bootm 0x40007FC0;\0" \ 100 "updatebackup=" \ 101 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ 102 "mmc dev 0 0\0" \ 103 "updatebootb=" \ 104 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ 105 "lpj=lpj=3981312\0" \ 106 "nfsboot=" \ 107 "setenv bootargs root=/dev/nfs rw " \ 108 "nfsroot=${nfsroot},nolock,tcp " \ 109 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 110 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ 111 "; run bootk\0" \ 112 "ramfsboot=" \ 113 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ 114 "${console} ${meminfo} " \ 115 "initrd=0x43000000,8M ramdisk=8192\0" \ 116 "mmcboot=" \ 117 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 118 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 119 "run bootk\0" \ 120 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ 121 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 122 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 123 "verify=n\0" \ 124 "rootfstype=ext4\0" \ 125 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 126 "meminfo=crashkernel=32M@0x50000000\0" \ 127 "nfsroot=/nfsroot/arm\0" \ 128 "bootblock=" CONFIG_BOOTBLOCK "\0" \ 129 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ 130 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 131 "${fdtfile}\0" \ 132 "mmcdev=0\0" \ 133 "mmcbootpart=2\0" \ 134 "mmcrootpart=5\0" \ 135 "opts=always_resume=1\0" \ 136 "partitions=" PARTS_DEFAULT \ 137 "dfu_alt_info=" CONFIG_DFU_ALT \ 138 "spladdr=0x40000100\0" \ 139 "splsize=0x200\0" \ 140 "splfile=falcon.bin\0" \ 141 "spl_export=" \ 142 "setexpr spl_imgsize ${splsize} + 8 ;" \ 143 "setenv spl_imgsize 0x${spl_imgsize};" \ 144 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 145 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 146 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 147 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 148 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 149 "spl export atags 0x40007FC0;" \ 150 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 151 "mw.l ${spl_addr_tmp} ${splsize};" \ 152 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 153 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 154 "setenv spl_imgsize;" \ 155 "setenv spl_imgaddr;" \ 156 "setenv spl_addr_tmp;\0" \ 157 CONFIG_EXTRA_ENV_ITB \ 158 "fdtaddr=40800000\0" \ 159 160 /* Falcon mode definitions */ 161 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 162 163 /* GPT */ 164 165 /* Security subsystem - enable hw_rand() */ 166 #define CONFIG_EXYNOS_ACE_SHA 167 168 /* Common misc for Samsung */ 169 #define CONFIG_MISC_COMMON 170 171 #define CONFIG_MISC_INIT_R 172 173 /* Download menu - Samsung common */ 174 #define CONFIG_LCD_MENU 175 176 /* Download menu - definitions for check keys */ 177 #ifndef __ASSEMBLY__ 178 179 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" 180 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 181 #define KEY_PWR_STATUS_MASK (1 << 0) 182 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 183 #define KEY_PWR_INTERRUPT_MASK (1 << 0) 184 185 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 186 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 187 #endif /* __ASSEMBLY__ */ 188 189 /* LCD console */ 190 #define LCD_BPP LCD_COLOR16 191 192 /* LCD */ 193 #define CONFIG_BMP_16BPP 194 #define CONFIG_FB_ADDR 0x52504000 195 #define CONFIG_EXYNOS_MIPI_DSIM 196 #define CONFIG_VIDEO_BMP_GZIP 197 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) 198 199 #endif /* __CONFIG_H */ 200