1c7964f86SEnric Balletbò i Serra /* 2c7964f86SEnric Balletbò i Serra * ti_omap3_common.h 3c7964f86SEnric Balletbò i Serra * 4c7964f86SEnric Balletbò i Serra * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5c7964f86SEnric Balletbò i Serra * 6c7964f86SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 7c7964f86SEnric Balletbò i Serra * 8c7964f86SEnric Balletbò i Serra * For more details, please see the technical documents listed at 9c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3530 10c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3630 11c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/dm3730 12c7964f86SEnric Balletbò i Serra */ 13c7964f86SEnric Balletbò i Serra 14c7964f86SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 15c7964f86SEnric Balletbò i Serra #define __CONFIG_TI_OMAP3_COMMON_H__ 16c7964f86SEnric Balletbò i Serra 17c7964f86SEnric Balletbò i Serra 18c7964f86SEnric Balletbò i Serra #include <asm/arch/cpu.h> 19987ec585SNishanth Menon #include <asm/arch/omap.h> 20c7964f86SEnric Balletbò i Serra 21b3f4ca11SSimon Glass #ifndef CONFIG_SPL_BUILD 22*c7b9686dSThomas Chou # define CONFIG_NS16550_SERIAL 23b3f4ca11SSimon Glass #endif 24b3f4ca11SSimon Glass 25c6f90e14SNishanth Menon /* Common ARM Erratas */ 26c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_454179 27c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_430973 28c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_621766 29c6f90e14SNishanth Menon 30c7964f86SEnric Balletbò i Serra /* The chip has SDRC controller */ 31c7964f86SEnric Balletbò i Serra #define CONFIG_SDRC 32c7964f86SEnric Balletbò i Serra 33c7964f86SEnric Balletbò i Serra /* Clock Defines */ 34c7964f86SEnric Balletbò i Serra #define V_OSCK 26000000 /* Clock output from T2 */ 35c7964f86SEnric Balletbò i Serra #define V_SCLK (V_OSCK >> 1) 36c7964f86SEnric Balletbò i Serra 37c7964f86SEnric Balletbò i Serra /* NS16550 Configuration */ 38c7964f86SEnric Balletbò i Serra #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 39c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550 40*c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 41b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 42c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_SERIAL 43c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_REG_SIZE (-4) 44b3f4ca11SSimon Glass #endif 45c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 46c7964f86SEnric Balletbò i Serra 115200} 47c7964f86SEnric Balletbò i Serra 48c7964f86SEnric Balletbò i Serra /* Select serial console configuration */ 49c7964f86SEnric Balletbò i Serra #define CONFIG_CONS_INDEX 3 50b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 51c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 52c7964f86SEnric Balletbò i Serra #define CONFIG_SERIAL3 3 53b3f4ca11SSimon Glass #endif 54c7964f86SEnric Balletbò i Serra 55c7964f86SEnric Balletbò i Serra /* Physical Memory Map */ 56c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 57c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 58c7964f86SEnric Balletbò i Serra 59c7964f86SEnric Balletbò i Serra /* 60c7964f86SEnric Balletbò i Serra * OMAP3 has 12 GP timers, they can be driven by the system clock 61c7964f86SEnric Balletbò i Serra * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 62c7964f86SEnric Balletbò i Serra * This rate is divided by a local divisor. 63c7964f86SEnric Balletbò i Serra */ 64c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 65c7964f86SEnric Balletbò i Serra 66c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_MONITOR_LEN (256 << 10) 67c7964f86SEnric Balletbò i Serra 68c7964f86SEnric Balletbò i Serra /* TWL4030 */ 69689821fdSIgor Grinberg #define CONFIG_TWL4030_POWER 70c7964f86SEnric Balletbò i Serra 71c7964f86SEnric Balletbò i Serra /* SPL */ 72c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40200800 73c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE (54 * 1024) 74c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 75c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_POWER_SUPPORT 76d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 77d3289aacSTom Rini (64 << 20)) 78d3289aacSTom Rini 79c7964f86SEnric Balletbò i Serra 80c7964f86SEnric Balletbò i Serra #ifdef CONFIG_NAND 81c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_NAND_SUPPORT 82c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_NAND_SIMPLE 83df4dbb5dSTom Rini #define CONFIG_SYS_NAND_BASE 0x30000000 84c7964f86SEnric Balletbò i Serra #endif 85c7964f86SEnric Balletbò i Serra 86c7964f86SEnric Balletbò i Serra /* Now bring in the rest of the common code. */ 879a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 88c7964f86SEnric Balletbò i Serra 89c7964f86SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 90