1c7964f86SEnric Balletbò i Serra /* 2c7964f86SEnric Balletbò i Serra * ti_omap3_common.h 3c7964f86SEnric Balletbò i Serra * 4c7964f86SEnric Balletbò i Serra * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5c7964f86SEnric Balletbò i Serra * 6c7964f86SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 7c7964f86SEnric Balletbò i Serra * 8c7964f86SEnric Balletbò i Serra * For more details, please see the technical documents listed at 9c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3530 10c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3630 11c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/dm3730 12c7964f86SEnric Balletbò i Serra */ 13c7964f86SEnric Balletbò i Serra 14c7964f86SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 15c7964f86SEnric Balletbò i Serra #define __CONFIG_TI_OMAP3_COMMON_H__ 16c7964f86SEnric Balletbò i Serra 17c7964f86SEnric Balletbò i Serra 18c7964f86SEnric Balletbò i Serra #include <asm/arch/cpu.h> 19*987ec585SNishanth Menon #include <asm/arch/omap.h> 20c7964f86SEnric Balletbò i Serra 21b3f4ca11SSimon Glass #ifndef CONFIG_SPL_BUILD 22b3f4ca11SSimon Glass # define CONFIG_OMAP_SERIAL 23b3f4ca11SSimon Glass #endif 24b3f4ca11SSimon Glass 25c7964f86SEnric Balletbò i Serra /* The chip has SDRC controller */ 26c7964f86SEnric Balletbò i Serra #define CONFIG_SDRC 27c7964f86SEnric Balletbò i Serra 28c7964f86SEnric Balletbò i Serra /* Clock Defines */ 29c7964f86SEnric Balletbò i Serra #define V_OSCK 26000000 /* Clock output from T2 */ 30c7964f86SEnric Balletbò i Serra #define V_SCLK (V_OSCK >> 1) 31c7964f86SEnric Balletbò i Serra 32c7964f86SEnric Balletbò i Serra /* NS16550 Configuration */ 33c7964f86SEnric Balletbò i Serra #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 34c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550 35b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 36c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_SERIAL 37c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_REG_SIZE (-4) 38c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 39b3f4ca11SSimon Glass #endif 40c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 41c7964f86SEnric Balletbò i Serra 115200} 42c7964f86SEnric Balletbò i Serra 43c7964f86SEnric Balletbò i Serra /* Select serial console configuration */ 44c7964f86SEnric Balletbò i Serra #define CONFIG_CONS_INDEX 3 45b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 46c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 47c7964f86SEnric Balletbò i Serra #define CONFIG_SERIAL3 3 48b3f4ca11SSimon Glass #endif 49c7964f86SEnric Balletbò i Serra 50c7964f86SEnric Balletbò i Serra /* Physical Memory Map */ 51c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 52c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 53c7964f86SEnric Balletbò i Serra 54c7964f86SEnric Balletbò i Serra /* 55c7964f86SEnric Balletbò i Serra * OMAP3 has 12 GP timers, they can be driven by the system clock 56c7964f86SEnric Balletbò i Serra * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 57c7964f86SEnric Balletbò i Serra * This rate is divided by a local divisor. 58c7964f86SEnric Balletbò i Serra */ 59c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 60c7964f86SEnric Balletbò i Serra 61c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_MONITOR_LEN (256 << 10) 62c7964f86SEnric Balletbò i Serra 63c7964f86SEnric Balletbò i Serra /* TWL4030 */ 64c7964f86SEnric Balletbò i Serra #define CONFIG_TWL4030_POWER 1 65c7964f86SEnric Balletbò i Serra 66c7964f86SEnric Balletbò i Serra /* SPL */ 67c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40200800 68c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE (54 * 1024) 69c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 70c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_POWER_SUPPORT 71d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 72d3289aacSTom Rini (64 << 20)) 73d3289aacSTom Rini 74c7964f86SEnric Balletbò i Serra 75c7964f86SEnric Balletbò i Serra #ifdef CONFIG_NAND 76c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_NAND_SUPPORT 77c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_NAND_SIMPLE 78df4dbb5dSTom Rini #define CONFIG_SYS_NAND_BASE 0x30000000 79c7964f86SEnric Balletbò i Serra #endif 80c7964f86SEnric Balletbò i Serra 81c7964f86SEnric Balletbò i Serra /* Now bring in the rest of the common code. */ 82c7964f86SEnric Balletbò i Serra #include <configs/ti_armv7_common.h> 83c7964f86SEnric Balletbò i Serra 84c7964f86SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 85