1 /* 2 * Common configuration header file for all Keystone II EVM platforms 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_KS2_EVM_H 11 #define __CONFIG_KS2_EVM_H 12 13 #define CONFIG_SOC_KEYSTONE 14 15 /* U-Boot Build Configuration */ 16 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ 17 #define CONFIG_BOARD_EARLY_INIT_F 18 #define CONFIG_DISPLAY_CPUINFO 19 20 /* SoC Configuration */ 21 #define CONFIG_ARCH_CPU_INIT 22 #define CONFIG_SYS_ARCH_TIMER 23 #define CONFIG_SYS_TEXT_BASE 0x0c000000 24 #define CONFIG_SPL_TARGET "u-boot-spi.gph" 25 #define CONFIG_SYS_DCACHE_OFF 26 27 /* Memory Configuration */ 28 #define CONFIG_NR_DRAM_BANKS 2 29 #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 30 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ 31 #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ 32 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ 33 GENERATED_GBL_DATA_SIZE) 34 35 #ifdef CONFIG_SYS_MALLOC_F_LEN 36 #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN 37 #else 38 #define SPL_MALLOC_F_SIZE 0 39 #endif 40 41 /* SPL SPI Loader Configuration */ 42 #define CONFIG_SPL_PAD_TO 65536 43 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) 44 #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ 45 CONFIG_SPL_MAX_SIZE) 46 #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) 47 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 48 CONFIG_SPL_BSS_MAX_SIZE) 49 #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) 50 #define CONFIG_SPL_STACK_SIZE (8 * 1024) 51 #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ 52 CONFIG_SYS_SPL_MALLOC_SIZE + \ 53 SPL_MALLOC_F_SIZE + \ 54 CONFIG_SPL_STACK_SIZE - 4) 55 #define CONFIG_SPL_SPI_FLASH_SUPPORT 56 #define CONFIG_SPL_SPI_SUPPORT 57 #define CONFIG_SPL_SPI_LOAD 58 #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO 59 60 /* UART Configuration */ 61 #define CONFIG_SYS_NS16550 62 #define CONFIG_SYS_NS16550_MEM32 63 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 64 #define CONFIG_SYS_NS16550_SERIAL 65 #define CONFIG_SYS_NS16550_REG_SIZE -4 66 #else 67 #define CONFIG_KEYSTONE_SERIAL 68 #endif 69 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE 70 #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE 71 #define CONFIG_CONS_INDEX 1 72 73 #ifndef CONFIG_SOC_K2G 74 #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) 75 #else 76 #define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2 77 #endif 78 79 /* SPI Configuration */ 80 #define CONFIG_SPI_FLASH_STMICRO 81 #define CONFIG_DAVINCI_SPI 82 #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) 83 #define CONFIG_SF_DEFAULT_SPEED 30000000 84 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 85 #define CONFIG_SYS_SPI0 86 #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE 87 #define CONFIG_SYS_SPI0_NUM_CS 4 88 #define CONFIG_SYS_SPI1 89 #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE 90 #define CONFIG_SYS_SPI1_NUM_CS 4 91 #define CONFIG_SYS_SPI2 92 #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE 93 #define CONFIG_SYS_SPI2_NUM_CS 4 94 95 /* Network Configuration */ 96 #define CONFIG_PHYLIB 97 #define CONFIG_PHY_MARVELL 98 #define CONFIG_MII 99 #define CONFIG_BOOTP_DEFAULT 100 #define CONFIG_BOOTP_DNS 101 #define CONFIG_BOOTP_DNS2 102 #define CONFIG_BOOTP_SEND_HOSTNAME 103 #define CONFIG_NET_RETRY_COUNT 32 104 #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 105 #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 106 #define CONFIG_SYS_SGMII_RATESCALE 2 107 108 /* Keyston Navigator Configuration */ 109 #define CONFIG_TI_KSNAV 110 #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS 111 #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE 112 #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE 113 #define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE 114 #define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE 115 #define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE 116 #define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE 117 #define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE 118 #define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE 119 #define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE 120 #define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE 121 #define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE 122 #define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM 123 #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM 124 125 /* NETCP pktdma */ 126 #define CONFIG_KSNAV_PKTDMA_NETCP 127 #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE 128 #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE 129 #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM 130 #define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE 131 #define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM 132 #define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE 133 #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE 134 #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM 135 #define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE 136 #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE 137 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE 138 139 /* Keystone net */ 140 #define CONFIG_DRIVER_TI_KEYSTONE_NET 141 #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR 142 #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE 143 #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE 144 #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE 145 #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES 146 147 /* SerDes */ 148 #define CONFIG_TI_KEYSTONE_SERDES 149 150 /* AEMIF */ 151 #define CONFIG_TI_AEMIF 152 #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE 153 154 /* I2C Configuration */ 155 #define CONFIG_SYS_I2C_DAVINCI 156 #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 157 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ 158 #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 159 #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ 160 #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 161 #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ 162 #define I2C_BUS_MAX 3 163 164 /* EEPROM definitions */ 165 #define CONFIG_SYS_I2C_MULTI_EEPROMS 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 167 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 169 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 170 #define CONFIG_ENV_EEPROM_IS_ON_I2C 171 172 /* NAND Configuration */ 173 #define CONFIG_NAND_DAVINCI 174 #define CONFIG_KEYSTONE_RBL_NAND 175 #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET 176 #define CONFIG_SYS_NAND_MASK_CLE 0x4000 177 #define CONFIG_SYS_NAND_MASK_ALE 0x2000 178 #define CONFIG_SYS_NAND_CS 2 179 #define CONFIG_SYS_NAND_USE_FLASH_BBT 180 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 181 182 #define CONFIG_SYS_NAND_LARGEPAGE 183 #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } 184 #define CONFIG_SYS_MAX_NAND_DEVICE 1 185 #define CONFIG_SYS_NAND_MAX_CHIPS 1 186 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 187 #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ 188 #define CONFIG_ENV_IS_IN_NAND 189 #define CONFIG_ENV_OFFSET 0x100000 190 #define CONFIG_MTD_PARTITIONS 191 #define CONFIG_RBTREE 192 #define CONFIG_LZO 193 #define MTDIDS_DEFAULT "nand0=davinci_nand.0" 194 #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ 195 "1024k(bootloader)ro,512k(params)ro," \ 196 "-(ubifs)" 197 198 /* USB Configuration */ 199 #define CONFIG_USB_XHCI 200 #define CONFIG_USB_XHCI_DWC3 201 #define CONFIG_USB_XHCI_KEYSTONE 202 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 203 #define CONFIG_EFI_PARTITION 204 #define CONFIG_FS_FAT 205 #define CONFIG_SYS_CACHELINE_SIZE 64 206 #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE 207 #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE 208 #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE 209 #define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE 210 211 /* U-Boot command configuration */ 212 #define CONFIG_CMD_DHCP 213 #define CONFIG_CMD_PING 214 #define CONFIG_CMD_SAVES 215 #define CONFIG_CMD_NAND 216 #define CONFIG_CMD_UBI 217 #define CONFIG_CMD_UBIFS 218 #define CONFIG_CMD_SF 219 #define CONFIG_CMD_EEPROM 220 #define CONFIG_CMD_USB 221 222 /* U-Boot general configuration */ 223 #define CONFIG_MISC_INIT_R 224 #define CONFIG_CRC32_VERIFY 225 #define CONFIG_MX_CYCLIC 226 #define CONFIG_TIMESTAMP 227 228 /* EDMA3 */ 229 #define CONFIG_TI_EDMA3 230 231 #define CONFIG_EXTRA_ENV_SETTINGS \ 232 DEFAULT_LINUX_BOOT_ENV \ 233 CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ 234 "boot=ubi\0" \ 235 "tftp_root=/\0" \ 236 "nfs_root=/export\0" \ 237 "mem_lpae=1\0" \ 238 "mem_reserve=512M\0" \ 239 "addr_ubi=0x82000000\0" \ 240 "addr_secdb_key=0xc000000\0" \ 241 "name_kern=zImage\0" \ 242 "run_mon=mon_install ${addr_mon}\0" \ 243 "run_kern=bootz ${loadaddr} - ${fdtaddr}\0" \ 244 "init_net=run args_all args_net\0" \ 245 "init_ubi=run args_all args_ubi; " \ 246 "ubi part ubifs; ubifsmount ubi:boot;" \ 247 "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ 248 "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ 249 "get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0" \ 250 "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ 251 "get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0" \ 252 "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 253 "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ 254 "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ 255 "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ 256 "sf write ${loadaddr} 0 ${filesize}\0" \ 257 "burn_uboot_nand=nand erase 0 0x100000; " \ 258 "nand write ${loadaddr} 0 ${filesize}\0" \ 259 "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ 260 "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ 261 "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ 262 "${nfs_options} ip=dhcp\0" \ 263 "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ 264 "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ 265 "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ 266 "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 267 "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ 268 "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ 269 "burn_ubi=nand erase.part ubifs; " \ 270 "nand write ${addr_ubi} ubifs ${filesize}\0" \ 271 "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ 272 "args_ramfs=setenv bootargs ${bootargs} " \ 273 "rdinit=/sbin/init rw root=/dev/ram0 " \ 274 "initrd=0x808080000,80M\0" \ 275 "no_post=1\0" \ 276 "mtdparts=mtdparts=davinci_nand.0:" \ 277 "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" 278 279 #define CONFIG_BOOTCOMMAND \ 280 "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ 281 "get_kern_${boot} run_mon run_kern" 282 283 #define CONFIG_BOOTARGS \ 284 285 /* Linux interfacing */ 286 #define CONFIG_OF_BOARD_SETUP 287 288 /* Now for the remaining common defines */ 289 #include <configs/ti_armv7_common.h> 290 291 /* We wont be loading up OS from SPL for now.. */ 292 #undef CONFIG_SPL_OS_BOOT 293 294 /* We do not have MMC support.. yet.. */ 295 #undef CONFIG_SPL_LIBDISK_SUPPORT 296 #undef CONFIG_SPL_MMC_SUPPORT 297 #undef CONFIG_SPL_FAT_SUPPORT 298 #undef CONFIG_SPL_EXT_SUPPORT 299 #undef CONFIG_MMC 300 #undef CONFIG_GENERIC_MMC 301 #undef CONFIG_CMD_MMC 302 303 /* And no support for GPIO, yet.. */ 304 #undef CONFIG_SPL_GPIO_SUPPORT 305 #undef CONFIG_CMD_GPIO 306 307 /* we may include files below only after all above definitions */ 308 #include <asm/arch/hardware.h> 309 #include <asm/arch/clock.h> 310 #ifndef CONFIG_SOC_K2G 311 #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) 312 #else 313 #define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk] 314 #endif 315 316 #endif /* __CONFIG_KS2_EVM_H */ 317