1*e8428d6fSNishanth Menon /* 2*e8428d6fSNishanth Menon * Common configuration header file for all Keystone II EVM platforms 3*e8428d6fSNishanth Menon * 4*e8428d6fSNishanth Menon * (C) Copyright 2012-2014 5*e8428d6fSNishanth Menon * Texas Instruments Incorporated, <www.ti.com> 6*e8428d6fSNishanth Menon * 7*e8428d6fSNishanth Menon * SPDX-License-Identifier: GPL-2.0+ 8*e8428d6fSNishanth Menon */ 9*e8428d6fSNishanth Menon 10*e8428d6fSNishanth Menon #ifndef __CONFIG_KS2_EVM_H 11*e8428d6fSNishanth Menon #define __CONFIG_KS2_EVM_H 12*e8428d6fSNishanth Menon 13*e8428d6fSNishanth Menon #define CONFIG_SOC_KEYSTONE 14*e8428d6fSNishanth Menon 15*e8428d6fSNishanth Menon /* U-Boot Build Configuration */ 16*e8428d6fSNishanth Menon #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ 17*e8428d6fSNishanth Menon #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ 18*e8428d6fSNishanth Menon #define CONFIG_SYS_CONSOLE_INFO_QUIET 19*e8428d6fSNishanth Menon #define CONFIG_BOARD_EARLY_INIT_F 20*e8428d6fSNishanth Menon #define CONFIG_SYS_THUMB_BUILD 21*e8428d6fSNishanth Menon 22*e8428d6fSNishanth Menon /* SoC Configuration */ 23*e8428d6fSNishanth Menon #define CONFIG_ARCH_CPU_INIT 24*e8428d6fSNishanth Menon #define CONFIG_SYS_ARCH_TIMER 25*e8428d6fSNishanth Menon #define CONFIG_SYS_TEXT_BASE 0x0c001000 26*e8428d6fSNishanth Menon #define CONFIG_SPL_TARGET "u-boot-spi.gph" 27*e8428d6fSNishanth Menon #define CONFIG_SYS_DCACHE_OFF 28*e8428d6fSNishanth Menon 29*e8428d6fSNishanth Menon /* Memory Configuration */ 30*e8428d6fSNishanth Menon #define CONFIG_NR_DRAM_BANKS 2 31*e8428d6fSNishanth Menon #define CONFIG_SYS_SDRAM_BASE 0x80000000 32*e8428d6fSNishanth Menon #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 33*e8428d6fSNishanth Menon #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ 34*e8428d6fSNishanth Menon #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ 35*e8428d6fSNishanth Menon #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ 36*e8428d6fSNishanth Menon #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ 37*e8428d6fSNishanth Menon GENERATED_GBL_DATA_SIZE) 38*e8428d6fSNishanth Menon 39*e8428d6fSNishanth Menon /* SPL SPI Loader Configuration */ 40*e8428d6fSNishanth Menon #define CONFIG_SPL_PAD_TO 65536 41*e8428d6fSNishanth Menon #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) 42*e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ 43*e8428d6fSNishanth Menon CONFIG_SPL_MAX_SIZE) 44*e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) 45*e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 46*e8428d6fSNishanth Menon CONFIG_SPL_BSS_MAX_SIZE) 47*e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) 48*e8428d6fSNishanth Menon #define CONFIG_SPL_STACK_SIZE (8 * 1024) 49*e8428d6fSNishanth Menon #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ 50*e8428d6fSNishanth Menon CONFIG_SYS_SPL_MALLOC_SIZE + \ 51*e8428d6fSNishanth Menon CONFIG_SPL_STACK_SIZE - 4) 52*e8428d6fSNishanth Menon #define CONFIG_SPL_LIBCOMMON_SUPPORT 53*e8428d6fSNishanth Menon #define CONFIG_SPL_LIBGENERIC_SUPPORT 54*e8428d6fSNishanth Menon #define CONFIG_SPL_SERIAL_SUPPORT 55*e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_FLASH_SUPPORT 56*e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_SUPPORT 57*e8428d6fSNishanth Menon #define CONFIG_SPL_BOARD_INIT 58*e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_LOAD 59*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO 60*e8428d6fSNishanth Menon #define CONFIG_SPL_FRAMEWORK 61*e8428d6fSNishanth Menon 62*e8428d6fSNishanth Menon /* UART Configuration */ 63*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550 64*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_SERIAL 65*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_MEM32 66*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_REG_SIZE -4 67*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE 68*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE 69*e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) 70*e8428d6fSNishanth Menon #define CONFIG_CONS_INDEX 1 71*e8428d6fSNishanth Menon #define CONFIG_BAUDRATE 115200 72*e8428d6fSNishanth Menon 73*e8428d6fSNishanth Menon /* SPI Configuration */ 74*e8428d6fSNishanth Menon #define CONFIG_SPI 75*e8428d6fSNishanth Menon #define CONFIG_SPI_FLASH_STMICRO 76*e8428d6fSNishanth Menon #define CONFIG_DAVINCI_SPI 77*e8428d6fSNishanth Menon #define CONFIG_CMD_SPI 78*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) 79*e8428d6fSNishanth Menon #define CONFIG_SF_DEFAULT_SPEED 30000000 80*e8428d6fSNishanth Menon #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 81*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0 82*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE 83*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0_NUM_CS 4 84*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1 85*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE 86*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_NUM_CS 4 87*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2 88*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE 89*e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_NUM_CS 4 90*e8428d6fSNishanth Menon 91*e8428d6fSNishanth Menon /* Network Configuration */ 92*e8428d6fSNishanth Menon #define CONFIG_PHYLIB 93*e8428d6fSNishanth Menon #define CONFIG_PHY_MARVELL 94*e8428d6fSNishanth Menon #define CONFIG_MII 95*e8428d6fSNishanth Menon #define CONFIG_BOOTP_DEFAULT 96*e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS 97*e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS2 98*e8428d6fSNishanth Menon #define CONFIG_BOOTP_SEND_HOSTNAME 99*e8428d6fSNishanth Menon #define CONFIG_NET_RETRY_COUNT 32 100*e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 101*e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 102*e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_RATESCALE 2 103*e8428d6fSNishanth Menon 104*e8428d6fSNishanth Menon /* Keyston Navigator Configuration */ 105*e8428d6fSNishanth Menon #define CONFIG_TI_KSNAV 106*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS 107*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE 108*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE 109*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE 110*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE 111*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE 112*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE 113*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE 114*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE 115*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE 116*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE 117*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE 118*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM 119*e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM 120*e8428d6fSNishanth Menon 121*e8428d6fSNishanth Menon /* NETCP pktdma */ 122*e8428d6fSNishanth Menon #define CONFIG_KSNAV_PKTDMA_NETCP 123*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE 124*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE 125*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM 126*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE 127*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM 128*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE 129*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE 130*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM 131*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE 132*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE 133*e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE 134*e8428d6fSNishanth Menon 135*e8428d6fSNishanth Menon /* Keystone net */ 136*e8428d6fSNishanth Menon #define CONFIG_DRIVER_TI_KEYSTONE_NET 137*e8428d6fSNishanth Menon #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR 138*e8428d6fSNishanth Menon #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE 139*e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE 140*e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE 141*e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES 142*e8428d6fSNishanth Menon 143*e8428d6fSNishanth Menon /* SerDes */ 144*e8428d6fSNishanth Menon #define CONFIG_TI_KEYSTONE_SERDES 145*e8428d6fSNishanth Menon 146*e8428d6fSNishanth Menon /* AEMIF */ 147*e8428d6fSNishanth Menon #define CONFIG_TI_AEMIF 148*e8428d6fSNishanth Menon #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE 149*e8428d6fSNishanth Menon 150*e8428d6fSNishanth Menon /* I2C Configuration */ 151*e8428d6fSNishanth Menon #define CONFIG_SYS_I2C 152*e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_DAVINCI 153*e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 154*e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ 155*e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 156*e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ 157*e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 158*e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ 159*e8428d6fSNishanth Menon #define I2C_BUS_MAX 3 160*e8428d6fSNishanth Menon 161*e8428d6fSNishanth Menon /* EEPROM definitions */ 162*e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_MULTI_EEPROMS 163*e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 164*e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 165*e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 166*e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 167*e8428d6fSNishanth Menon #define CONFIG_ENV_EEPROM_IS_ON_I2C 168*e8428d6fSNishanth Menon 169*e8428d6fSNishanth Menon /* NAND Configuration */ 170*e8428d6fSNishanth Menon #define CONFIG_NAND_DAVINCI 171*e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_RBL_NAND 172*e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET 173*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_CLE 0x4000 174*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_ALE 0x2000 175*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_CS 2 176*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_USE_FLASH_BBT 177*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 178*e8428d6fSNishanth Menon 179*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_LARGEPAGE 180*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } 181*e8428d6fSNishanth Menon #define CONFIG_SYS_MAX_NAND_DEVICE 1 182*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MAX_CHIPS 1 183*e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 184*e8428d6fSNishanth Menon #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ 185*e8428d6fSNishanth Menon #define CONFIG_ENV_IS_IN_NAND 186*e8428d6fSNishanth Menon #define CONFIG_ENV_OFFSET 0x100000 187*e8428d6fSNishanth Menon #define CONFIG_MTD_PARTITIONS 188*e8428d6fSNishanth Menon #define CONFIG_MTD_DEVICE 189*e8428d6fSNishanth Menon #define CONFIG_RBTREE 190*e8428d6fSNishanth Menon #define CONFIG_LZO 191*e8428d6fSNishanth Menon #define MTDIDS_DEFAULT "nand0=davinci_nand.0" 192*e8428d6fSNishanth Menon #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ 193*e8428d6fSNishanth Menon "1024k(bootloader)ro,512k(params)ro," \ 194*e8428d6fSNishanth Menon "-(ubifs)" 195*e8428d6fSNishanth Menon 196*e8428d6fSNishanth Menon /* USB Configuration */ 197*e8428d6fSNishanth Menon #define CONFIG_USB_XHCI 198*e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_DWC3 199*e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_KEYSTONE 200*e8428d6fSNishanth Menon #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 201*e8428d6fSNishanth Menon #define CONFIG_USB_STORAGE 202*e8428d6fSNishanth Menon #define CONFIG_DOS_PARTITION 203*e8428d6fSNishanth Menon #define CONFIG_EFI_PARTITION 204*e8428d6fSNishanth Menon #define CONFIG_FS_FAT 205*e8428d6fSNishanth Menon #define CONFIG_SYS_CACHELINE_SIZE 64 206*e8428d6fSNishanth Menon #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE 207*e8428d6fSNishanth Menon #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE 208*e8428d6fSNishanth Menon #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE 209*e8428d6fSNishanth Menon #define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE 210*e8428d6fSNishanth Menon 211*e8428d6fSNishanth Menon /* U-Boot command configuration */ 212*e8428d6fSNishanth Menon #define CONFIG_CMD_ASKENV 213*e8428d6fSNishanth Menon #define CONFIG_CMD_DHCP 214*e8428d6fSNishanth Menon #define CONFIG_CMD_I2C 215*e8428d6fSNishanth Menon #define CONFIG_CMD_PING 216*e8428d6fSNishanth Menon #define CONFIG_CMD_SAVES 217*e8428d6fSNishanth Menon #define CONFIG_CMD_MTDPARTS 218*e8428d6fSNishanth Menon #define CONFIG_CMD_NAND 219*e8428d6fSNishanth Menon #define CONFIG_CMD_UBI 220*e8428d6fSNishanth Menon #define CONFIG_CMD_UBIFS 221*e8428d6fSNishanth Menon #define CONFIG_CMD_SF 222*e8428d6fSNishanth Menon #define CONFIG_CMD_EEPROM 223*e8428d6fSNishanth Menon #define CONFIG_CMD_USB 224*e8428d6fSNishanth Menon #define CONFIG_CMD_FAT 225*e8428d6fSNishanth Menon #define CONFIG_CMD_FS_GENERIC 226*e8428d6fSNishanth Menon 227*e8428d6fSNishanth Menon /* U-Boot general configuration */ 228*e8428d6fSNishanth Menon #define CONFIG_SYS_GENERIC_BOARD 229*e8428d6fSNishanth Menon #define CONFIG_MISC_INIT_R 230*e8428d6fSNishanth Menon #define CONFIG_SYS_CBSIZE 1024 231*e8428d6fSNishanth Menon #define CONFIG_SYS_PBSIZE 2048 232*e8428d6fSNishanth Menon #define CONFIG_SYS_MAXARGS 16 233*e8428d6fSNishanth Menon #define CONFIG_SYS_HUSH_PARSER 234*e8428d6fSNishanth Menon #define CONFIG_SYS_LONGHELP 235*e8428d6fSNishanth Menon #define CONFIG_CRC32_VERIFY 236*e8428d6fSNishanth Menon #define CONFIG_MX_CYCLIC 237*e8428d6fSNishanth Menon #define CONFIG_CMDLINE_EDITING 238*e8428d6fSNishanth Menon #define CONFIG_VERSION_VARIABLE 239*e8428d6fSNishanth Menon #define CONFIG_TIMESTAMP 240*e8428d6fSNishanth Menon 241*e8428d6fSNishanth Menon /* EDMA3 */ 242*e8428d6fSNishanth Menon #define CONFIG_TI_EDMA3 243*e8428d6fSNishanth Menon 244*e8428d6fSNishanth Menon #define CONFIG_BOOTDELAY 3 245*e8428d6fSNishanth Menon #define CONFIG_BOOTFILE "uImage" 246*e8428d6fSNishanth Menon #define CONFIG_EXTRA_ENV_SETTINGS \ 247*e8428d6fSNishanth Menon CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ 248*e8428d6fSNishanth Menon "boot=ubi\0" \ 249*e8428d6fSNishanth Menon "tftp_root=/\0" \ 250*e8428d6fSNishanth Menon "nfs_root=/export\0" \ 251*e8428d6fSNishanth Menon "mem_lpae=1\0" \ 252*e8428d6fSNishanth Menon "mem_reserve=512M\0" \ 253*e8428d6fSNishanth Menon "addr_fdt=0x87000000\0" \ 254*e8428d6fSNishanth Menon "addr_kern=0x88000000\0" \ 255*e8428d6fSNishanth Menon "addr_uboot=0x87000000\0" \ 256*e8428d6fSNishanth Menon "addr_fs=0x82000000\0" \ 257*e8428d6fSNishanth Menon "addr_ubi=0x82000000\0" \ 258*e8428d6fSNishanth Menon "addr_secdb_key=0xc000000\0" \ 259*e8428d6fSNishanth Menon "fdt_high=0xffffffff\0" \ 260*e8428d6fSNishanth Menon "name_kern=uImage-keystone-evm.bin\0" \ 261*e8428d6fSNishanth Menon "run_mon=mon_install ${addr_mon}\0" \ 262*e8428d6fSNishanth Menon "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ 263*e8428d6fSNishanth Menon "init_net=run args_all args_net\0" \ 264*e8428d6fSNishanth Menon "init_ubi=run args_all args_ubi; " \ 265*e8428d6fSNishanth Menon "ubi part ubifs; ubifsmount ubi:boot;" \ 266*e8428d6fSNishanth Menon "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ 267*e8428d6fSNishanth Menon "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ 268*e8428d6fSNishanth Menon "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ 269*e8428d6fSNishanth Menon "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ 270*e8428d6fSNishanth Menon "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ 271*e8428d6fSNishanth Menon "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 272*e8428d6fSNishanth Menon "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ 273*e8428d6fSNishanth Menon "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ 274*e8428d6fSNishanth Menon "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ 275*e8428d6fSNishanth Menon "sf write ${addr_uboot} 0 ${filesize}\0" \ 276*e8428d6fSNishanth Menon "burn_uboot_nand=nand erase 0 0x100000; " \ 277*e8428d6fSNishanth Menon "nand write ${addr_uboot} 0 ${filesize}\0" \ 278*e8428d6fSNishanth Menon "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ 279*e8428d6fSNishanth Menon "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ 280*e8428d6fSNishanth Menon "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ 281*e8428d6fSNishanth Menon "${nfs_options} ip=dhcp\0" \ 282*e8428d6fSNishanth Menon "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ 283*e8428d6fSNishanth Menon "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ 284*e8428d6fSNishanth Menon "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ 285*e8428d6fSNishanth Menon "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 286*e8428d6fSNishanth Menon "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ 287*e8428d6fSNishanth Menon "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ 288*e8428d6fSNishanth Menon "burn_ubi=nand erase.part ubifs; " \ 289*e8428d6fSNishanth Menon "nand write ${addr_ubi} ubifs ${filesize}\0" \ 290*e8428d6fSNishanth Menon "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ 291*e8428d6fSNishanth Menon "args_ramfs=setenv bootargs ${bootargs} " \ 292*e8428d6fSNishanth Menon "rdinit=/sbin/init rw root=/dev/ram0 " \ 293*e8428d6fSNishanth Menon "initrd=0x802000000,9M\0" \ 294*e8428d6fSNishanth Menon "no_post=1\0" \ 295*e8428d6fSNishanth Menon "mtdparts=mtdparts=davinci_nand.0:" \ 296*e8428d6fSNishanth Menon "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" 297*e8428d6fSNishanth Menon 298*e8428d6fSNishanth Menon #define CONFIG_BOOTCOMMAND \ 299*e8428d6fSNishanth Menon "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ 300*e8428d6fSNishanth Menon "get_kern_${boot} run_mon run_kern" 301*e8428d6fSNishanth Menon 302*e8428d6fSNishanth Menon #define CONFIG_BOOTARGS \ 303*e8428d6fSNishanth Menon 304*e8428d6fSNishanth Menon /* Linux interfacing */ 305*e8428d6fSNishanth Menon #define CONFIG_CMDLINE_TAG 306*e8428d6fSNishanth Menon #define CONFIG_SETUP_MEMORY_TAGS 307*e8428d6fSNishanth Menon #define CONFIG_OF_LIBFDT 1 308*e8428d6fSNishanth Menon #define CONFIG_OF_BOARD_SETUP 309*e8428d6fSNishanth Menon #define CONFIG_SYS_BARGSIZE 1024 310*e8428d6fSNishanth Menon #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) 311*e8428d6fSNishanth Menon 312*e8428d6fSNishanth Menon #define CONFIG_SUPPORT_RAW_INITRD 313*e8428d6fSNishanth Menon 314*e8428d6fSNishanth Menon /* we may include files below only after all above definitions */ 315*e8428d6fSNishanth Menon #include <asm/arch/hardware.h> 316*e8428d6fSNishanth Menon #include <asm/arch/clock.h> 317*e8428d6fSNishanth Menon #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) 318*e8428d6fSNishanth Menon 319*e8428d6fSNishanth Menon #endif /* __CONFIG_KS2_EVM_H */ 320