1e8428d6fSNishanth Menon /*
2e8428d6fSNishanth Menon  * Common configuration header file for all Keystone II EVM platforms
3e8428d6fSNishanth Menon  *
4e8428d6fSNishanth Menon  * (C) Copyright 2012-2014
5e8428d6fSNishanth Menon  *     Texas Instruments Incorporated, <www.ti.com>
6e8428d6fSNishanth Menon  *
7e8428d6fSNishanth Menon  * SPDX-License-Identifier:     GPL-2.0+
8e8428d6fSNishanth Menon  */
9e8428d6fSNishanth Menon 
10e8428d6fSNishanth Menon #ifndef __CONFIG_KS2_EVM_H
11e8428d6fSNishanth Menon #define __CONFIG_KS2_EVM_H
12e8428d6fSNishanth Menon 
13e8428d6fSNishanth Menon #define CONFIG_SOC_KEYSTONE
14e8428d6fSNishanth Menon 
15e8428d6fSNishanth Menon /* U-Boot Build Configuration */
16e8428d6fSNishanth Menon #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
17e8428d6fSNishanth Menon #define CONFIG_BOARD_EARLY_INIT_F
18e8428d6fSNishanth Menon 
19e8428d6fSNishanth Menon /* SoC Configuration */
20e8428d6fSNishanth Menon #define CONFIG_ARCH_CPU_INIT
21e8428d6fSNishanth Menon #define CONFIG_SYS_ARCH_TIMER
22e8428d6fSNishanth Menon #define CONFIG_SYS_TEXT_BASE		0x0c001000
23e8428d6fSNishanth Menon #define CONFIG_SPL_TARGET		"u-boot-spi.gph"
24e8428d6fSNishanth Menon #define CONFIG_SYS_DCACHE_OFF
25e8428d6fSNishanth Menon 
26e8428d6fSNishanth Menon /* Memory Configuration */
27e8428d6fSNishanth Menon #define CONFIG_NR_DRAM_BANKS		2
28e8428d6fSNishanth Menon #define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
29e8428d6fSNishanth Menon #define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
30e8428d6fSNishanth Menon #define CONFIG_STACKSIZE		(512 << 10)     /* 512 KiB */
31e8428d6fSNishanth Menon #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - \
32e8428d6fSNishanth Menon 					GENERATED_GBL_DATA_SIZE)
33e8428d6fSNishanth Menon 
34e8428d6fSNishanth Menon /* SPL SPI Loader Configuration */
35e8428d6fSNishanth Menon #define CONFIG_SPL_PAD_TO		65536
36e8428d6fSNishanth Menon #define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_PAD_TO - 8)
37e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SPL_TEXT_BASE + \
38e8428d6fSNishanth Menon 					CONFIG_SPL_MAX_SIZE)
39e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_MAX_SIZE		(32 * 1024)
40e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
41e8428d6fSNishanth Menon 					CONFIG_SPL_BSS_MAX_SIZE)
42e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_SIZE	(32 * 1024)
43e8428d6fSNishanth Menon #define CONFIG_SPL_STACK_SIZE		(8 * 1024)
44e8428d6fSNishanth Menon #define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START + \
45e8428d6fSNishanth Menon 					CONFIG_SYS_SPL_MALLOC_SIZE + \
46e8428d6fSNishanth Menon 					CONFIG_SPL_STACK_SIZE - 4)
47e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_FLASH_SUPPORT
48e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_SUPPORT
49e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_LOAD
50e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
51e8428d6fSNishanth Menon 
52e8428d6fSNishanth Menon /* UART Configuration */
53e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550
54e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_SERIAL
55e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_MEM32
56e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_REG_SIZE	-4
57e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
58e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
59e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_CLK		clk_get_rate(KS2_CLK1_6)
60e8428d6fSNishanth Menon #define CONFIG_CONS_INDEX		1
61e8428d6fSNishanth Menon 
62e8428d6fSNishanth Menon /* SPI Configuration */
63e8428d6fSNishanth Menon #define CONFIG_SPI_FLASH_STMICRO
64e8428d6fSNishanth Menon #define CONFIG_DAVINCI_SPI
65e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_CLK		clk_get_rate(KS2_CLK1_6)
66e8428d6fSNishanth Menon #define CONFIG_SF_DEFAULT_SPEED		30000000
67e8428d6fSNishanth Menon #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
68e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0
69e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_BASE		KS2_SPI0_BASE
70e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0_NUM_CS		4
71e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1
72e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_BASE		KS2_SPI1_BASE
73e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_NUM_CS		4
74e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2
75e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
76e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_NUM_CS		4
77e8428d6fSNishanth Menon 
78e8428d6fSNishanth Menon /* Network Configuration */
79e8428d6fSNishanth Menon #define CONFIG_PHYLIB
80e8428d6fSNishanth Menon #define CONFIG_PHY_MARVELL
81e8428d6fSNishanth Menon #define CONFIG_MII
82e8428d6fSNishanth Menon #define CONFIG_BOOTP_DEFAULT
83e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS
84e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS2
85e8428d6fSNishanth Menon #define CONFIG_BOOTP_SEND_HOSTNAME
86e8428d6fSNishanth Menon #define CONFIG_NET_RETRY_COUNT		32
87e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_REFCLK_MHZ	312
88e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
89e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_RATESCALE	2
90e8428d6fSNishanth Menon 
91e8428d6fSNishanth Menon /* Keyston Navigator Configuration */
92e8428d6fSNishanth Menon #define CONFIG_TI_KSNAV
93e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
94e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
95e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
96e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_STATUS_RAM_BASE		KS2_QM_STATUS_RAM_BASE
97e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_INTD_CONF_BASE		KS2_QM_INTD_CONF_BASE
98e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CMD_BASE		KS2_QM_PDSP1_CMD_BASE
99e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE		KS2_QM_PDSP1_CTRL_BASE
100e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE		KS2_QM_PDSP1_IRAM_BASE
101e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE	KS2_QM_MANAGER_QUEUES_BASE
102e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE	KS2_QM_MANAGER_Q_PROXY_BASE
103e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE	KS2_QM_QUEUE_STATUS_BASE
104e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_LINK_RAM_BASE		KS2_QM_LINK_RAM_BASE
105e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_REGION_NUM		KS2_QM_REGION_NUM
106e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM
107e8428d6fSNishanth Menon 
108e8428d6fSNishanth Menon /* NETCP pktdma */
109e8428d6fSNishanth Menon #define CONFIG_KSNAV_PKTDMA_NETCP
110e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
111e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
112e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
113e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_BASE		KS2_NETCP_PDMA_RX_BASE
114e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM	KS2_NETCP_PDMA_RX_CH_NUM
115e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE	KS2_NETCP_PDMA_SCHED_BASE
116e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE	KS2_NETCP_PDMA_RX_FLOW_BASE
117e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM	KS2_NETCP_PDMA_RX_FLOW_NUM
118e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE	KS2_NETCP_PDMA_RX_FREE_QUEUE
119e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
120e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
121e8428d6fSNishanth Menon 
122e8428d6fSNishanth Menon /* Keystone net */
123e8428d6fSNishanth Menon #define CONFIG_DRIVER_TI_KEYSTONE_NET
124e8428d6fSNishanth Menon #define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
125e8428d6fSNishanth Menon #define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
126e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
127e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
128e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES
129e8428d6fSNishanth Menon 
130e8428d6fSNishanth Menon /* SerDes */
131e8428d6fSNishanth Menon #define CONFIG_TI_KEYSTONE_SERDES
132e8428d6fSNishanth Menon 
133e8428d6fSNishanth Menon /* AEMIF */
134e8428d6fSNishanth Menon #define CONFIG_TI_AEMIF
135e8428d6fSNishanth Menon #define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
136e8428d6fSNishanth Menon 
137e8428d6fSNishanth Menon /* I2C Configuration */
138e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_DAVINCI
139e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED	100000
140e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE	0x10 /* SMBus host address */
141e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED1	100000
142e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE1	0x10 /* SMBus host address */
143e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED2	100000
144e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE2	0x10 /* SMBus host address */
145e8428d6fSNishanth Menon #define I2C_BUS_MAX			3
146e8428d6fSNishanth Menon 
147e8428d6fSNishanth Menon /* EEPROM definitions */
148e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_MULTI_EEPROMS
149e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
150e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
151e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
152e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
153e8428d6fSNishanth Menon #define CONFIG_ENV_EEPROM_IS_ON_I2C
154e8428d6fSNishanth Menon 
155e8428d6fSNishanth Menon /* NAND Configuration */
156e8428d6fSNishanth Menon #define CONFIG_NAND_DAVINCI
157e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_RBL_NAND
158e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
159e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_CLE		0x4000
160e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_ALE		0x2000
161e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_CS			2
162e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_USE_FLASH_BBT
163e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
164e8428d6fSNishanth Menon 
165e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_LARGEPAGE
166e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
167e8428d6fSNishanth Menon #define CONFIG_SYS_MAX_NAND_DEVICE		1
168e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MAX_CHIPS		1
169e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
170e8428d6fSNishanth Menon #define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
171e8428d6fSNishanth Menon #define CONFIG_ENV_IS_IN_NAND
172e8428d6fSNishanth Menon #define CONFIG_ENV_OFFSET			0x100000
173e8428d6fSNishanth Menon #define CONFIG_MTD_PARTITIONS
174e8428d6fSNishanth Menon #define CONFIG_RBTREE
175e8428d6fSNishanth Menon #define CONFIG_LZO
176e8428d6fSNishanth Menon #define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
177e8428d6fSNishanth Menon #define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:" \
178e8428d6fSNishanth Menon 					"1024k(bootloader)ro,512k(params)ro," \
179e8428d6fSNishanth Menon 					"-(ubifs)"
180e8428d6fSNishanth Menon 
181e8428d6fSNishanth Menon /* USB Configuration */
182e8428d6fSNishanth Menon #define CONFIG_USB_XHCI
183e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_DWC3
184e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_KEYSTONE
185e8428d6fSNishanth Menon #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
186e8428d6fSNishanth Menon #define CONFIG_EFI_PARTITION
187e8428d6fSNishanth Menon #define CONFIG_FS_FAT
188e8428d6fSNishanth Menon #define CONFIG_SYS_CACHELINE_SIZE		64
189e8428d6fSNishanth Menon #define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
190e8428d6fSNishanth Menon #define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
191e8428d6fSNishanth Menon #define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE
192e8428d6fSNishanth Menon #define CONFIG_USB_PHY_CFG_BASE			KS2_USB_PHY_CFG_BASE
193e8428d6fSNishanth Menon 
194e8428d6fSNishanth Menon /* U-Boot command configuration */
195e8428d6fSNishanth Menon #define CONFIG_CMD_DHCP
196e8428d6fSNishanth Menon #define CONFIG_CMD_PING
197e8428d6fSNishanth Menon #define CONFIG_CMD_SAVES
198e8428d6fSNishanth Menon #define CONFIG_CMD_NAND
199e8428d6fSNishanth Menon #define CONFIG_CMD_UBI
200e8428d6fSNishanth Menon #define CONFIG_CMD_UBIFS
201e8428d6fSNishanth Menon #define CONFIG_CMD_SF
202e8428d6fSNishanth Menon #define CONFIG_CMD_EEPROM
203e8428d6fSNishanth Menon #define CONFIG_CMD_USB
204e8428d6fSNishanth Menon 
205e8428d6fSNishanth Menon /* U-Boot general configuration */
206e8428d6fSNishanth Menon #define CONFIG_MISC_INIT_R
207e8428d6fSNishanth Menon #define CONFIG_CRC32_VERIFY
208e8428d6fSNishanth Menon #define CONFIG_MX_CYCLIC
209e8428d6fSNishanth Menon #define CONFIG_TIMESTAMP
210e8428d6fSNishanth Menon 
211e8428d6fSNishanth Menon /* EDMA3 */
212e8428d6fSNishanth Menon #define CONFIG_TI_EDMA3
213e8428d6fSNishanth Menon 
214e8428d6fSNishanth Menon #define CONFIG_BOOTFILE			"uImage"
215e8428d6fSNishanth Menon #define CONFIG_EXTRA_ENV_SETTINGS					\
216e8428d6fSNishanth Menon 	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
217e8428d6fSNishanth Menon 	"boot=ubi\0"							\
218e8428d6fSNishanth Menon 	"tftp_root=/\0"							\
219e8428d6fSNishanth Menon 	"nfs_root=/export\0"						\
220e8428d6fSNishanth Menon 	"mem_lpae=1\0"							\
221e8428d6fSNishanth Menon 	"mem_reserve=512M\0"						\
222e8428d6fSNishanth Menon 	"addr_fdt=0x87000000\0"						\
223e8428d6fSNishanth Menon 	"addr_kern=0x88000000\0"					\
224e8428d6fSNishanth Menon 	"addr_uboot=0x87000000\0"					\
225e8428d6fSNishanth Menon 	"addr_fs=0x82000000\0"						\
226e8428d6fSNishanth Menon 	"addr_ubi=0x82000000\0"						\
227e8428d6fSNishanth Menon 	"addr_secdb_key=0xc000000\0"					\
228e8428d6fSNishanth Menon 	"fdt_high=0xffffffff\0"						\
229e8428d6fSNishanth Menon 	"name_kern=uImage-keystone-evm.bin\0"				\
230e8428d6fSNishanth Menon 	"run_mon=mon_install ${addr_mon}\0"				\
231e8428d6fSNishanth Menon 	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0"			\
232e8428d6fSNishanth Menon 	"init_net=run args_all args_net\0"				\
233e8428d6fSNishanth Menon 	"init_ubi=run args_all args_ubi; "				\
234e8428d6fSNishanth Menon 		"ubi part ubifs; ubifsmount ubi:boot;"			\
235e8428d6fSNishanth Menon 		"ubifsload ${addr_secdb_key} securedb.key.bin;\0"       \
236e8428d6fSNishanth Menon 	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
237e8428d6fSNishanth Menon 	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0"		\
238e8428d6fSNishanth Menon 	"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
239e8428d6fSNishanth Menon 	"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0"		\
240e8428d6fSNishanth Menon 	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
241e8428d6fSNishanth Menon 	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
242e8428d6fSNishanth Menon 	"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0"	\
243e8428d6fSNishanth Menon 	"burn_uboot_spi=sf probe; sf erase 0 0x100000; "		\
244e8428d6fSNishanth Menon 		"sf write ${addr_uboot} 0 ${filesize}\0"		\
245e8428d6fSNishanth Menon 	"burn_uboot_nand=nand erase 0 0x100000; "			\
246e8428d6fSNishanth Menon 		"nand write ${addr_uboot} 0 ${filesize}\0"		\
247e8428d6fSNishanth Menon 	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
248e8428d6fSNishanth Menon 	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
249e8428d6fSNishanth Menon 		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
250e8428d6fSNishanth Menon 		"${nfs_options} ip=dhcp\0"				\
251e8428d6fSNishanth Menon 	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
252e8428d6fSNishanth Menon 	"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
253e8428d6fSNishanth Menon 	"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
254e8428d6fSNishanth Menon 	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
255e8428d6fSNishanth Menon 	"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0"	\
256e8428d6fSNishanth Menon 	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
257e8428d6fSNishanth Menon 	"burn_ubi=nand erase.part ubifs; "				\
258e8428d6fSNishanth Menon 		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
259e8428d6fSNishanth Menon 	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
260e8428d6fSNishanth Menon 	"args_ramfs=setenv bootargs ${bootargs} "			\
261e8428d6fSNishanth Menon 		"rdinit=/sbin/init rw root=/dev/ram0 "			\
262e8428d6fSNishanth Menon 		"initrd=0x802000000,9M\0"				\
263e8428d6fSNishanth Menon 	"no_post=1\0"							\
264e8428d6fSNishanth Menon 	"mtdparts=mtdparts=davinci_nand.0:"				\
265e8428d6fSNishanth Menon 		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
266e8428d6fSNishanth Menon 
267e8428d6fSNishanth Menon #define CONFIG_BOOTCOMMAND						\
268e8428d6fSNishanth Menon 	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
269e8428d6fSNishanth Menon 		"get_kern_${boot} run_mon run_kern"
270e8428d6fSNishanth Menon 
271e8428d6fSNishanth Menon #define CONFIG_BOOTARGS							\
272e8428d6fSNishanth Menon 
273e8428d6fSNishanth Menon /* Linux interfacing */
274e8428d6fSNishanth Menon #define CONFIG_OF_BOARD_SETUP
275e8428d6fSNishanth Menon 
276*e07cff11SNishanth Menon /* Now for the remaining common defines */
277*e07cff11SNishanth Menon #include <configs/ti_armv7_common.h>
278*e07cff11SNishanth Menon 
279*e07cff11SNishanth Menon /* We wont be loading up OS from SPL for now.. */
280*e07cff11SNishanth Menon #undef CONFIG_SPL_OS_BOOT
281*e07cff11SNishanth Menon 
282*e07cff11SNishanth Menon /* We do not have MMC support.. yet.. */
283*e07cff11SNishanth Menon #undef CONFIG_SPL_LIBDISK_SUPPORT
284*e07cff11SNishanth Menon #undef CONFIG_SPL_MMC_SUPPORT
285*e07cff11SNishanth Menon #undef CONFIG_SPL_FAT_SUPPORT
286*e07cff11SNishanth Menon #undef CONFIG_SPL_EXT_SUPPORT
287*e07cff11SNishanth Menon #undef CONFIG_MMC
288*e07cff11SNishanth Menon #undef CONFIG_GENERIC_MMC
289*e07cff11SNishanth Menon #undef CONFIG_CMD_MMC
290*e07cff11SNishanth Menon 
291*e07cff11SNishanth Menon /* And no support for GPIO, yet.. */
292*e07cff11SNishanth Menon #undef CONFIG_SPL_GPIO_SUPPORT
293*e07cff11SNishanth Menon #undef CONFIG_CMD_GPIO
294e8428d6fSNishanth Menon 
295e8428d6fSNishanth Menon /* we may include files below only after all above definitions */
296e8428d6fSNishanth Menon #include <asm/arch/hardware.h>
297e8428d6fSNishanth Menon #include <asm/arch/clock.h>
298e8428d6fSNishanth Menon #define CONFIG_SYS_HZ_CLOCK		clk_get_rate(KS2_CLK1_6)
299e8428d6fSNishanth Menon 
300e8428d6fSNishanth Menon #endif /* __CONFIG_KS2_EVM_H */
301