1e8428d6fSNishanth Menon /* 2e8428d6fSNishanth Menon * Common configuration header file for all Keystone II EVM platforms 3e8428d6fSNishanth Menon * 4e8428d6fSNishanth Menon * (C) Copyright 2012-2014 5e8428d6fSNishanth Menon * Texas Instruments Incorporated, <www.ti.com> 6e8428d6fSNishanth Menon * 7e8428d6fSNishanth Menon * SPDX-License-Identifier: GPL-2.0+ 8e8428d6fSNishanth Menon */ 9e8428d6fSNishanth Menon 10e8428d6fSNishanth Menon #ifndef __CONFIG_KS2_EVM_H 11e8428d6fSNishanth Menon #define __CONFIG_KS2_EVM_H 12e8428d6fSNishanth Menon 13e8428d6fSNishanth Menon #define CONFIG_SOC_KEYSTONE 14e8428d6fSNishanth Menon 15e8428d6fSNishanth Menon /* U-Boot Build Configuration */ 16e8428d6fSNishanth Menon #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ 17e8428d6fSNishanth Menon 18e8428d6fSNishanth Menon /* SoC Configuration */ 19e8428d6fSNishanth Menon #define CONFIG_ARCH_CPU_INIT 20e8428d6fSNishanth Menon #define CONFIG_SYS_ARCH_TIMER 2127ce6965SVitaly Andrianov #ifndef CONFIG_SYS_TEXT_BASE 22401f2d91SLokesh Vutla #define CONFIG_SYS_TEXT_BASE 0x0c000000 2327ce6965SVitaly Andrianov #endif 24e8428d6fSNishanth Menon #define CONFIG_SPL_TARGET "u-boot-spi.gph" 25e8428d6fSNishanth Menon #define CONFIG_SYS_DCACHE_OFF 26e8428d6fSNishanth Menon 27e8428d6fSNishanth Menon /* Memory Configuration */ 28e8428d6fSNishanth Menon #define CONFIG_NR_DRAM_BANKS 2 29e8428d6fSNishanth Menon #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 30e8428d6fSNishanth Menon #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ 31e8428d6fSNishanth Menon #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ 32401f2d91SLokesh Vutla #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ 33e8428d6fSNishanth Menon GENERATED_GBL_DATA_SIZE) 34e8428d6fSNishanth Menon 35aaf461f9SLokesh Vutla #ifdef CONFIG_SYS_MALLOC_F_LEN 36aaf461f9SLokesh Vutla #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN 37aaf461f9SLokesh Vutla #else 38aaf461f9SLokesh Vutla #define SPL_MALLOC_F_SIZE 0 39aaf461f9SLokesh Vutla #endif 40aaf461f9SLokesh Vutla 41e8428d6fSNishanth Menon /* SPL SPI Loader Configuration */ 42e8428d6fSNishanth Menon #define CONFIG_SPL_PAD_TO 65536 43e8428d6fSNishanth Menon #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) 44e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ 45e8428d6fSNishanth Menon CONFIG_SPL_MAX_SIZE) 46e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) 47e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 48e8428d6fSNishanth Menon CONFIG_SPL_BSS_MAX_SIZE) 49e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) 508ccdba8bSPhil Edworthy #define KEYSTONE_SPL_STACK_SIZE (8 * 1024) 51e8428d6fSNishanth Menon #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ 52e8428d6fSNishanth Menon CONFIG_SYS_SPL_MALLOC_SIZE + \ 53aaf461f9SLokesh Vutla SPL_MALLOC_F_SIZE + \ 548ccdba8bSPhil Edworthy KEYSTONE_SPL_STACK_SIZE - 4) 55e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_LOAD 56e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO 57e8428d6fSNishanth Menon 58*a4562d06SFranklin S Cooper Jr /* SRAM scratch space entries */ 59*a4562d06SFranklin S Cooper Jr #define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 60*a4562d06SFranklin S Cooper Jr 61*a4562d06SFranklin S Cooper Jr #define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) 62*a4562d06SFranklin S Cooper Jr #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) 63*a4562d06SFranklin S Cooper Jr #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) 64*a4562d06SFranklin S Cooper Jr 65e8428d6fSNishanth Menon /* UART Configuration */ 66e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_MEM32 67391839fbSLokesh Vutla #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 68391839fbSLokesh Vutla #define CONFIG_SYS_NS16550_SERIAL 69e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_REG_SIZE -4 70391839fbSLokesh Vutla #endif 71e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE 72e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE 73e8428d6fSNishanth Menon #define CONFIG_CONS_INDEX 1 74e8428d6fSNishanth Menon 75e6d71e1cSVitaly Andrianov #ifndef CONFIG_SOC_K2G 7643ebbfc3SMasahiro Yamada #define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) 77e6d71e1cSVitaly Andrianov #else 7843ebbfc3SMasahiro Yamada #define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 79e6d71e1cSVitaly Andrianov #endif 80e6d71e1cSVitaly Andrianov 81e8428d6fSNishanth Menon /* SPI Configuration */ 82e8428d6fSNishanth Menon #define CONFIG_DAVINCI_SPI 8343ebbfc3SMasahiro Yamada #define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) 84e8428d6fSNishanth Menon #define CONFIG_SF_DEFAULT_SPEED 30000000 85e8428d6fSNishanth Menon #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 86e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0 87e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE 88e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0_NUM_CS 4 89e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1 90e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE 91e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_NUM_CS 4 92e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2 93e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE 94e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_NUM_CS 4 9539832244SVignesh R #ifdef CONFIG_SPL_BUILD 9639832244SVignesh R #undef CONFIG_DM_SPI 9739832244SVignesh R #undef CONFIG_DM_SPI_FLASH 9839832244SVignesh R #endif 99e8428d6fSNishanth Menon 100e8428d6fSNishanth Menon /* Network Configuration */ 101e8428d6fSNishanth Menon #define CONFIG_PHYLIB 102e8428d6fSNishanth Menon #define CONFIG_PHY_MARVELL 103e8428d6fSNishanth Menon #define CONFIG_MII 104e8428d6fSNishanth Menon #define CONFIG_BOOTP_DEFAULT 105e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS 106e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS2 107e8428d6fSNishanth Menon #define CONFIG_BOOTP_SEND_HOSTNAME 108e8428d6fSNishanth Menon #define CONFIG_NET_RETRY_COUNT 32 109e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 110e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 111e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_RATESCALE 2 112e8428d6fSNishanth Menon 113e8428d6fSNishanth Menon /* Keyston Navigator Configuration */ 114e8428d6fSNishanth Menon #define CONFIG_TI_KSNAV 115e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS 116e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE 117e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE 118e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE 119e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE 120e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE 121e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE 122e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE 123e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE 124e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE 125e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE 126e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE 127e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM 128e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM 129e8428d6fSNishanth Menon 130e8428d6fSNishanth Menon /* NETCP pktdma */ 131e8428d6fSNishanth Menon #define CONFIG_KSNAV_PKTDMA_NETCP 132e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE 133e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE 134e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM 135e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE 136e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM 137e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE 138e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE 139e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM 140e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE 141e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE 142e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE 143e8428d6fSNishanth Menon 144e8428d6fSNishanth Menon /* Keystone net */ 145e8428d6fSNishanth Menon #define CONFIG_DRIVER_TI_KEYSTONE_NET 146e8428d6fSNishanth Menon #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR 147e8428d6fSNishanth Menon #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE 148e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE 149e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE 150e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES 151e8428d6fSNishanth Menon 152e8428d6fSNishanth Menon /* SerDes */ 153e8428d6fSNishanth Menon #define CONFIG_TI_KEYSTONE_SERDES 154e8428d6fSNishanth Menon 155e8428d6fSNishanth Menon #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE 156e8428d6fSNishanth Menon 157e8428d6fSNishanth Menon /* I2C Configuration */ 158e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_DAVINCI 159e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 160e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ 161e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 162e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ 163e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 164e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ 165e8428d6fSNishanth Menon #define I2C_BUS_MAX 3 166e8428d6fSNishanth Menon 167e8428d6fSNishanth Menon /* EEPROM definitions */ 168e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 169e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 170e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 171e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 172e8428d6fSNishanth Menon #define CONFIG_ENV_EEPROM_IS_ON_I2C 173e8428d6fSNishanth Menon 174e8428d6fSNishanth Menon /* NAND Configuration */ 175e8428d6fSNishanth Menon #define CONFIG_NAND_DAVINCI 176e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_RBL_NAND 177e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET 178e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_CLE 0x4000 179e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_ALE 0x2000 180e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_CS 2 181e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_USE_FLASH_BBT 182e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 183e8428d6fSNishanth Menon 184e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_LARGEPAGE 185e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } 186e8428d6fSNishanth Menon #define CONFIG_SYS_MAX_NAND_DEVICE 1 187e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MAX_CHIPS 1 188e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 189e8428d6fSNishanth Menon #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ 190e8428d6fSNishanth Menon #define CONFIG_ENV_IS_IN_NAND 191e8428d6fSNishanth Menon #define CONFIG_ENV_OFFSET 0x100000 192e8428d6fSNishanth Menon #define CONFIG_MTD_PARTITIONS 193e8428d6fSNishanth Menon #define CONFIG_RBTREE 194e8428d6fSNishanth Menon #define CONFIG_LZO 195e8428d6fSNishanth Menon #define MTDIDS_DEFAULT "nand0=davinci_nand.0" 196e8428d6fSNishanth Menon #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ 197e8428d6fSNishanth Menon "1024k(bootloader)ro,512k(params)ro," \ 198e8428d6fSNishanth Menon "-(ubifs)" 199e8428d6fSNishanth Menon 200e8428d6fSNishanth Menon /* USB Configuration */ 201e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_KEYSTONE 202e8428d6fSNishanth Menon #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 203e8428d6fSNishanth Menon #define CONFIG_FS_FAT 204e8428d6fSNishanth Menon #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE 205e8428d6fSNishanth Menon #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE 206e8428d6fSNishanth Menon #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE 207e8428d6fSNishanth Menon #define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE 208e8428d6fSNishanth Menon 209e8428d6fSNishanth Menon /* U-Boot command configuration */ 210e8428d6fSNishanth Menon #define CONFIG_CMD_SAVES 211e8428d6fSNishanth Menon #define CONFIG_CMD_UBIFS 212e8428d6fSNishanth Menon #define CONFIG_CMD_EEPROM 213e8428d6fSNishanth Menon 214e8428d6fSNishanth Menon /* U-Boot general configuration */ 215e8428d6fSNishanth Menon #define CONFIG_MISC_INIT_R 216e8428d6fSNishanth Menon #define CONFIG_CRC32_VERIFY 217e8428d6fSNishanth Menon #define CONFIG_MX_CYCLIC 218e8428d6fSNishanth Menon #define CONFIG_TIMESTAMP 219e8428d6fSNishanth Menon 220e8428d6fSNishanth Menon /* EDMA3 */ 221e8428d6fSNishanth Menon #define CONFIG_TI_EDMA3 222e8428d6fSNishanth Menon 223abca9477SMurali Karicheri #define DEFAULT_FW_INITRAMFS_BOOT_ENV \ 224abca9477SMurali Karicheri "name_fw_rd=k2-fw-initrd.cpio.gz\0" \ 225abca9477SMurali Karicheri "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ 226abca9477SMurali Karicheri "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \ 227abca9477SMurali Karicheri "run set_rd_spec\0" \ 228979a1f8bSAndrew F. Davis "init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \ 229979a1f8bSAndrew F. Davis "run set_rd_spec\0" \ 230abca9477SMurali Karicheri "init_fw_rd_ramfs=setenv rd_spec -\0" \ 231abca9477SMurali Karicheri "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \ 232abca9477SMurali Karicheri "run set_rd_spec\0" \ 233abca9477SMurali Karicheri 2346f6e9439SNishanth Menon #define DEFAULT_PMMC_BOOT_ENV \ 2356f6e9439SNishanth Menon "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \ 2366f6e9439SNishanth Menon "dev_pmmc=0\0" \ 2376f6e9439SNishanth Menon "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \ 238979a1f8bSAndrew F. Davis "get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \ 2396f6e9439SNishanth Menon "get_pmmc_ramfs=run get_pmmc_net\0" \ 2406f6e9439SNishanth Menon "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \ 2416f6e9439SNishanth Menon "${bootdir}/${name_pmmc}\0" \ 2426f6e9439SNishanth Menon "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \ 2436f6e9439SNishanth Menon "run_pmmc=rproc init; rproc list; " \ 2446f6e9439SNishanth Menon "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ 2456f6e9439SNishanth Menon "rproc start ${dev_pmmc}\0" \ 2466f6e9439SNishanth Menon 247e8428d6fSNishanth Menon #define CONFIG_EXTRA_ENV_SETTINGS \ 248fd72d318SNishanth Menon DEFAULT_LINUX_BOOT_ENV \ 249e8428d6fSNishanth Menon CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ 25048dc1657SCarlos Hernandez "bootdir=/boot\0" \ 251e8428d6fSNishanth Menon "tftp_root=/\0" \ 252e8428d6fSNishanth Menon "nfs_root=/export\0" \ 253e8428d6fSNishanth Menon "mem_lpae=1\0" \ 254e8428d6fSNishanth Menon "addr_ubi=0x82000000\0" \ 255e8428d6fSNishanth Menon "addr_secdb_key=0xc000000\0" \ 256bad773f4SNishanth Menon "name_kern=zImage\0" \ 257ceee15ceSLokesh Vutla "addr_mon=0x87000000\0" \ 258e8428d6fSNishanth Menon "run_mon=mon_install ${addr_mon}\0" \ 259abca9477SMurali Karicheri "run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ 260e8428d6fSNishanth Menon "init_net=run args_all args_net\0" \ 261c29a3ce4SAndrew F. Davis "init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \ 262e8428d6fSNishanth Menon "init_ubi=run args_all args_ubi; " \ 2638462cb57SCarlos Hernandez "ubi part ubifs; ubifsmount ubi:rootfs;\0" \ 264fd72d318SNishanth Menon "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ 265c29a3ce4SAndrew F. Davis "get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \ 26648dc1657SCarlos Hernandez "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \ 267fd72d318SNishanth Menon "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ 268c29a3ce4SAndrew F. Davis "get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \ 26948dc1657SCarlos Hernandez "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \ 270e8428d6fSNishanth Menon "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 271c29a3ce4SAndrew F. Davis "get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \ 27248dc1657SCarlos Hernandez "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \ 2738889e984SVitaly Andrianov "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ 274c29a3ce4SAndrew F. Davis "get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \ 2757ec2328dSCooper Jr., Franklin "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \ 2768889e984SVitaly Andrianov "sf write ${loadaddr} 0 ${filesize}\0" \ 277e8428d6fSNishanth Menon "burn_uboot_nand=nand erase 0 0x100000; " \ 2788889e984SVitaly Andrianov "nand write ${loadaddr} 0 ${filesize}\0" \ 279e8428d6fSNishanth Menon "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ 280e8428d6fSNishanth Menon "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ 281e8428d6fSNishanth Menon "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ 282e8428d6fSNishanth Menon "${nfs_options} ip=dhcp\0" \ 283e8428d6fSNishanth Menon "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ 284fd72d318SNishanth Menon "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ 285fd72d318SNishanth Menon "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ 286e8428d6fSNishanth Menon "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 287fd72d318SNishanth Menon "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ 288e8428d6fSNishanth Menon "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ 289c29a3ce4SAndrew F. Davis "get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \ 290e8428d6fSNishanth Menon "burn_ubi=nand erase.part ubifs; " \ 291e8428d6fSNishanth Menon "nand write ${addr_ubi} ubifs ${filesize}\0" \ 292e8428d6fSNishanth Menon "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ 293e8428d6fSNishanth Menon "args_ramfs=setenv bootargs ${bootargs} " \ 294e8428d6fSNishanth Menon "rdinit=/sbin/init rw root=/dev/ram0 " \ 295f06b454bSVitaly Andrianov "initrd=0x808080000,80M\0" \ 296e8428d6fSNishanth Menon "no_post=1\0" \ 297e8428d6fSNishanth Menon "mtdparts=mtdparts=davinci_nand.0:" \ 298e8428d6fSNishanth Menon "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" 299e8428d6fSNishanth Menon 3006f6e9439SNishanth Menon #ifndef CONFIG_BOOTCOMMAND 301e8428d6fSNishanth Menon #define CONFIG_BOOTCOMMAND \ 302ceee15ceSLokesh Vutla "run init_${boot} get_mon_${boot} run_mon init_fw_rd_${boot} " \ 303ceee15ceSLokesh Vutla "get_fdt_${boot} get_kern_${boot} run_kern" 3046f6e9439SNishanth Menon #endif 305e8428d6fSNishanth Menon 306e8428d6fSNishanth Menon #define CONFIG_BOOTARGS \ 307e8428d6fSNishanth Menon 308e07cff11SNishanth Menon /* Now for the remaining common defines */ 309e07cff11SNishanth Menon #include <configs/ti_armv7_common.h> 310e07cff11SNishanth Menon 311e8428d6fSNishanth Menon /* we may include files below only after all above definitions */ 312e8428d6fSNishanth Menon #include <asm/arch/hardware.h> 313e8428d6fSNishanth Menon #include <asm/arch/clock.h> 314e6d71e1cSVitaly Andrianov #ifndef CONFIG_SOC_K2G 31543ebbfc3SMasahiro Yamada #define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) 316e6d71e1cSVitaly Andrianov #else 317e6d71e1cSVitaly Andrianov #define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk] 318e6d71e1cSVitaly Andrianov #endif 319e8428d6fSNishanth Menon 320e8428d6fSNishanth Menon #endif /* __CONFIG_KS2_EVM_H */ 321