1e8428d6fSNishanth Menon /* 2e8428d6fSNishanth Menon * Common configuration header file for all Keystone II EVM platforms 3e8428d6fSNishanth Menon * 4e8428d6fSNishanth Menon * (C) Copyright 2012-2014 5e8428d6fSNishanth Menon * Texas Instruments Incorporated, <www.ti.com> 6e8428d6fSNishanth Menon * 7e8428d6fSNishanth Menon * SPDX-License-Identifier: GPL-2.0+ 8e8428d6fSNishanth Menon */ 9e8428d6fSNishanth Menon 10e8428d6fSNishanth Menon #ifndef __CONFIG_KS2_EVM_H 11e8428d6fSNishanth Menon #define __CONFIG_KS2_EVM_H 12e8428d6fSNishanth Menon 13e8428d6fSNishanth Menon #define CONFIG_SOC_KEYSTONE 14e8428d6fSNishanth Menon 15e8428d6fSNishanth Menon /* U-Boot Build Configuration */ 16e8428d6fSNishanth Menon #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ 17e8428d6fSNishanth Menon #define CONFIG_BOARD_EARLY_INIT_F 18aeabe652SLokesh Vutla #define CONFIG_DISPLAY_CPUINFO 19e8428d6fSNishanth Menon 20e8428d6fSNishanth Menon /* SoC Configuration */ 21e8428d6fSNishanth Menon #define CONFIG_ARCH_CPU_INIT 22e8428d6fSNishanth Menon #define CONFIG_SYS_ARCH_TIMER 23401f2d91SLokesh Vutla #define CONFIG_SYS_TEXT_BASE 0x0c000000 24e8428d6fSNishanth Menon #define CONFIG_SPL_TARGET "u-boot-spi.gph" 25e8428d6fSNishanth Menon #define CONFIG_SYS_DCACHE_OFF 26e8428d6fSNishanth Menon 27e8428d6fSNishanth Menon /* Memory Configuration */ 28e8428d6fSNishanth Menon #define CONFIG_NR_DRAM_BANKS 2 29e8428d6fSNishanth Menon #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 30e8428d6fSNishanth Menon #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ 31e8428d6fSNishanth Menon #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ 32401f2d91SLokesh Vutla #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ 33e8428d6fSNishanth Menon GENERATED_GBL_DATA_SIZE) 34e8428d6fSNishanth Menon 35aaf461f9SLokesh Vutla #ifdef CONFIG_SYS_MALLOC_F_LEN 36aaf461f9SLokesh Vutla #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN 37aaf461f9SLokesh Vutla #else 38aaf461f9SLokesh Vutla #define SPL_MALLOC_F_SIZE 0 39aaf461f9SLokesh Vutla #endif 40aaf461f9SLokesh Vutla 41e8428d6fSNishanth Menon /* SPL SPI Loader Configuration */ 42e8428d6fSNishanth Menon #define CONFIG_SPL_PAD_TO 65536 43e8428d6fSNishanth Menon #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) 44e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ 45e8428d6fSNishanth Menon CONFIG_SPL_MAX_SIZE) 46e8428d6fSNishanth Menon #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) 47e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 48e8428d6fSNishanth Menon CONFIG_SPL_BSS_MAX_SIZE) 49e8428d6fSNishanth Menon #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) 50e8428d6fSNishanth Menon #define CONFIG_SPL_STACK_SIZE (8 * 1024) 51e8428d6fSNishanth Menon #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ 52e8428d6fSNishanth Menon CONFIG_SYS_SPL_MALLOC_SIZE + \ 53aaf461f9SLokesh Vutla SPL_MALLOC_F_SIZE + \ 54e8428d6fSNishanth Menon CONFIG_SPL_STACK_SIZE - 4) 55e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_FLASH_SUPPORT 56e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_SUPPORT 57e8428d6fSNishanth Menon #define CONFIG_SPL_SPI_LOAD 58e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO 59e8428d6fSNishanth Menon 60e8428d6fSNishanth Menon /* UART Configuration */ 61e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550 62e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_MEM32 63*391839fbSLokesh Vutla #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 64*391839fbSLokesh Vutla #define CONFIG_SYS_NS16550_SERIAL 65e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_REG_SIZE -4 66*391839fbSLokesh Vutla #else 67*391839fbSLokesh Vutla #define CONFIG_KEYSTONE_SERIAL 68*391839fbSLokesh Vutla #endif 69e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE 70e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE 71e8428d6fSNishanth Menon #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) 72e8428d6fSNishanth Menon #define CONFIG_CONS_INDEX 1 73e8428d6fSNishanth Menon 74e8428d6fSNishanth Menon /* SPI Configuration */ 75e8428d6fSNishanth Menon #define CONFIG_SPI_FLASH_STMICRO 76e8428d6fSNishanth Menon #define CONFIG_DAVINCI_SPI 77e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) 78e8428d6fSNishanth Menon #define CONFIG_SF_DEFAULT_SPEED 30000000 79e8428d6fSNishanth Menon #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 80e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0 81e8428d6fSNishanth Menon #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE 82e8428d6fSNishanth Menon #define CONFIG_SYS_SPI0_NUM_CS 4 83e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1 84e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE 85e8428d6fSNishanth Menon #define CONFIG_SYS_SPI1_NUM_CS 4 86e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2 87e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE 88e8428d6fSNishanth Menon #define CONFIG_SYS_SPI2_NUM_CS 4 89e8428d6fSNishanth Menon 90e8428d6fSNishanth Menon /* Network Configuration */ 91e8428d6fSNishanth Menon #define CONFIG_PHYLIB 92e8428d6fSNishanth Menon #define CONFIG_PHY_MARVELL 93e8428d6fSNishanth Menon #define CONFIG_MII 94e8428d6fSNishanth Menon #define CONFIG_BOOTP_DEFAULT 95e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS 96e8428d6fSNishanth Menon #define CONFIG_BOOTP_DNS2 97e8428d6fSNishanth Menon #define CONFIG_BOOTP_SEND_HOSTNAME 98e8428d6fSNishanth Menon #define CONFIG_NET_RETRY_COUNT 32 99e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 100e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 101e8428d6fSNishanth Menon #define CONFIG_SYS_SGMII_RATESCALE 2 102e8428d6fSNishanth Menon 103e8428d6fSNishanth Menon /* Keyston Navigator Configuration */ 104e8428d6fSNishanth Menon #define CONFIG_TI_KSNAV 105e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS 106e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE 107e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE 108e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE 109e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE 110e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE 111e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE 112e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE 113e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE 114e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE 115e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE 116e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE 117e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM 118e8428d6fSNishanth Menon #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM 119e8428d6fSNishanth Menon 120e8428d6fSNishanth Menon /* NETCP pktdma */ 121e8428d6fSNishanth Menon #define CONFIG_KSNAV_PKTDMA_NETCP 122e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE 123e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE 124e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM 125e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE 126e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM 127e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE 128e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE 129e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM 130e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE 131e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE 132e8428d6fSNishanth Menon #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE 133e8428d6fSNishanth Menon 134e8428d6fSNishanth Menon /* Keystone net */ 135e8428d6fSNishanth Menon #define CONFIG_DRIVER_TI_KEYSTONE_NET 136e8428d6fSNishanth Menon #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR 137e8428d6fSNishanth Menon #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE 138e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE 139e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE 140e8428d6fSNishanth Menon #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES 141e8428d6fSNishanth Menon 142e8428d6fSNishanth Menon /* SerDes */ 143e8428d6fSNishanth Menon #define CONFIG_TI_KEYSTONE_SERDES 144e8428d6fSNishanth Menon 145e8428d6fSNishanth Menon /* AEMIF */ 146e8428d6fSNishanth Menon #define CONFIG_TI_AEMIF 147e8428d6fSNishanth Menon #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE 148e8428d6fSNishanth Menon 149e8428d6fSNishanth Menon /* I2C Configuration */ 150e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_DAVINCI 151e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 152e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ 153e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 154e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ 155e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 156e8428d6fSNishanth Menon #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ 157e8428d6fSNishanth Menon #define I2C_BUS_MAX 3 158e8428d6fSNishanth Menon 159e8428d6fSNishanth Menon /* EEPROM definitions */ 160e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_MULTI_EEPROMS 161e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 162e8428d6fSNishanth Menon #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 163e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 164e8428d6fSNishanth Menon #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 165e8428d6fSNishanth Menon #define CONFIG_ENV_EEPROM_IS_ON_I2C 166e8428d6fSNishanth Menon 167e8428d6fSNishanth Menon /* NAND Configuration */ 168e8428d6fSNishanth Menon #define CONFIG_NAND_DAVINCI 169e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_RBL_NAND 170e8428d6fSNishanth Menon #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET 171e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_CLE 0x4000 172e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MASK_ALE 0x2000 173e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_CS 2 174e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_USE_FLASH_BBT 175e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 176e8428d6fSNishanth Menon 177e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_LARGEPAGE 178e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } 179e8428d6fSNishanth Menon #define CONFIG_SYS_MAX_NAND_DEVICE 1 180e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_MAX_CHIPS 1 181e8428d6fSNishanth Menon #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 182e8428d6fSNishanth Menon #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ 183e8428d6fSNishanth Menon #define CONFIG_ENV_IS_IN_NAND 184e8428d6fSNishanth Menon #define CONFIG_ENV_OFFSET 0x100000 185e8428d6fSNishanth Menon #define CONFIG_MTD_PARTITIONS 186e8428d6fSNishanth Menon #define CONFIG_RBTREE 187e8428d6fSNishanth Menon #define CONFIG_LZO 188e8428d6fSNishanth Menon #define MTDIDS_DEFAULT "nand0=davinci_nand.0" 189e8428d6fSNishanth Menon #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ 190e8428d6fSNishanth Menon "1024k(bootloader)ro,512k(params)ro," \ 191e8428d6fSNishanth Menon "-(ubifs)" 192e8428d6fSNishanth Menon 193e8428d6fSNishanth Menon /* USB Configuration */ 194e8428d6fSNishanth Menon #define CONFIG_USB_XHCI 195e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_DWC3 196e8428d6fSNishanth Menon #define CONFIG_USB_XHCI_KEYSTONE 197e8428d6fSNishanth Menon #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 198e8428d6fSNishanth Menon #define CONFIG_EFI_PARTITION 199e8428d6fSNishanth Menon #define CONFIG_FS_FAT 200e8428d6fSNishanth Menon #define CONFIG_SYS_CACHELINE_SIZE 64 201e8428d6fSNishanth Menon #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE 202e8428d6fSNishanth Menon #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE 203e8428d6fSNishanth Menon #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE 204e8428d6fSNishanth Menon #define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE 205e8428d6fSNishanth Menon 206e8428d6fSNishanth Menon /* U-Boot command configuration */ 207e8428d6fSNishanth Menon #define CONFIG_CMD_DHCP 208e8428d6fSNishanth Menon #define CONFIG_CMD_PING 209e8428d6fSNishanth Menon #define CONFIG_CMD_SAVES 210e8428d6fSNishanth Menon #define CONFIG_CMD_NAND 211e8428d6fSNishanth Menon #define CONFIG_CMD_UBI 212e8428d6fSNishanth Menon #define CONFIG_CMD_UBIFS 213e8428d6fSNishanth Menon #define CONFIG_CMD_SF 214e8428d6fSNishanth Menon #define CONFIG_CMD_EEPROM 215e8428d6fSNishanth Menon #define CONFIG_CMD_USB 216e8428d6fSNishanth Menon 217e8428d6fSNishanth Menon /* U-Boot general configuration */ 218e8428d6fSNishanth Menon #define CONFIG_MISC_INIT_R 219e8428d6fSNishanth Menon #define CONFIG_CRC32_VERIFY 220e8428d6fSNishanth Menon #define CONFIG_MX_CYCLIC 221e8428d6fSNishanth Menon #define CONFIG_TIMESTAMP 222e8428d6fSNishanth Menon 223e8428d6fSNishanth Menon /* EDMA3 */ 224e8428d6fSNishanth Menon #define CONFIG_TI_EDMA3 225e8428d6fSNishanth Menon 226e8428d6fSNishanth Menon #define CONFIG_EXTRA_ENV_SETTINGS \ 227fd72d318SNishanth Menon DEFAULT_LINUX_BOOT_ENV \ 228e8428d6fSNishanth Menon CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ 229e8428d6fSNishanth Menon "boot=ubi\0" \ 230e8428d6fSNishanth Menon "tftp_root=/\0" \ 231e8428d6fSNishanth Menon "nfs_root=/export\0" \ 232e8428d6fSNishanth Menon "mem_lpae=1\0" \ 233e8428d6fSNishanth Menon "mem_reserve=512M\0" \ 234e8428d6fSNishanth Menon "addr_ubi=0x82000000\0" \ 235e8428d6fSNishanth Menon "addr_secdb_key=0xc000000\0" \ 236bad773f4SNishanth Menon "name_kern=zImage\0" \ 237e8428d6fSNishanth Menon "run_mon=mon_install ${addr_mon}\0" \ 238bad773f4SNishanth Menon "run_kern=bootz ${loadaddr} - ${fdtaddr}\0" \ 239e8428d6fSNishanth Menon "init_net=run args_all args_net\0" \ 240e8428d6fSNishanth Menon "init_ubi=run args_all args_ubi; " \ 241e8428d6fSNishanth Menon "ubi part ubifs; ubifsmount ubi:boot;" \ 242e8428d6fSNishanth Menon "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ 243fd72d318SNishanth Menon "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ 244fd72d318SNishanth Menon "get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0" \ 245fd72d318SNishanth Menon "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ 246fd72d318SNishanth Menon "get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0" \ 247e8428d6fSNishanth Menon "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 248e8428d6fSNishanth Menon "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ 2498889e984SVitaly Andrianov "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ 250e8428d6fSNishanth Menon "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ 2518889e984SVitaly Andrianov "sf write ${loadaddr} 0 ${filesize}\0" \ 252e8428d6fSNishanth Menon "burn_uboot_nand=nand erase 0 0x100000; " \ 2538889e984SVitaly Andrianov "nand write ${loadaddr} 0 ${filesize}\0" \ 254e8428d6fSNishanth Menon "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ 255e8428d6fSNishanth Menon "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ 256e8428d6fSNishanth Menon "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ 257e8428d6fSNishanth Menon "${nfs_options} ip=dhcp\0" \ 258e8428d6fSNishanth Menon "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ 259fd72d318SNishanth Menon "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ 260fd72d318SNishanth Menon "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ 261e8428d6fSNishanth Menon "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ 262fd72d318SNishanth Menon "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ 263e8428d6fSNishanth Menon "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ 264e8428d6fSNishanth Menon "burn_ubi=nand erase.part ubifs; " \ 265e8428d6fSNishanth Menon "nand write ${addr_ubi} ubifs ${filesize}\0" \ 266e8428d6fSNishanth Menon "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ 267e8428d6fSNishanth Menon "args_ramfs=setenv bootargs ${bootargs} " \ 268e8428d6fSNishanth Menon "rdinit=/sbin/init rw root=/dev/ram0 " \ 269f06b454bSVitaly Andrianov "initrd=0x808080000,80M\0" \ 270e8428d6fSNishanth Menon "no_post=1\0" \ 271e8428d6fSNishanth Menon "mtdparts=mtdparts=davinci_nand.0:" \ 272e8428d6fSNishanth Menon "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" 273e8428d6fSNishanth Menon 274e8428d6fSNishanth Menon #define CONFIG_BOOTCOMMAND \ 275e8428d6fSNishanth Menon "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ 276e8428d6fSNishanth Menon "get_kern_${boot} run_mon run_kern" 277e8428d6fSNishanth Menon 278e8428d6fSNishanth Menon #define CONFIG_BOOTARGS \ 279e8428d6fSNishanth Menon 280e8428d6fSNishanth Menon /* Linux interfacing */ 281e8428d6fSNishanth Menon #define CONFIG_OF_BOARD_SETUP 282e8428d6fSNishanth Menon 283e07cff11SNishanth Menon /* Now for the remaining common defines */ 284e07cff11SNishanth Menon #include <configs/ti_armv7_common.h> 285e07cff11SNishanth Menon 286e07cff11SNishanth Menon /* We wont be loading up OS from SPL for now.. */ 287e07cff11SNishanth Menon #undef CONFIG_SPL_OS_BOOT 288e07cff11SNishanth Menon 289e07cff11SNishanth Menon /* We do not have MMC support.. yet.. */ 290e07cff11SNishanth Menon #undef CONFIG_SPL_LIBDISK_SUPPORT 291e07cff11SNishanth Menon #undef CONFIG_SPL_MMC_SUPPORT 292e07cff11SNishanth Menon #undef CONFIG_SPL_FAT_SUPPORT 293e07cff11SNishanth Menon #undef CONFIG_SPL_EXT_SUPPORT 294e07cff11SNishanth Menon #undef CONFIG_MMC 295e07cff11SNishanth Menon #undef CONFIG_GENERIC_MMC 296e07cff11SNishanth Menon #undef CONFIG_CMD_MMC 297e07cff11SNishanth Menon 298e07cff11SNishanth Menon /* And no support for GPIO, yet.. */ 299e07cff11SNishanth Menon #undef CONFIG_SPL_GPIO_SUPPORT 300e07cff11SNishanth Menon #undef CONFIG_CMD_GPIO 301e8428d6fSNishanth Menon 302e8428d6fSNishanth Menon /* we may include files below only after all above definitions */ 303e8428d6fSNishanth Menon #include <asm/arch/hardware.h> 304e8428d6fSNishanth Menon #include <asm/arch/clock.h> 305e8428d6fSNishanth Menon #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) 306e8428d6fSNishanth Menon 307e8428d6fSNishanth Menon #endif /* __CONFIG_KS2_EVM_H */ 308