187694558STom Rini /* 287694558STom Rini * ti_armv7_common.h 387694558STom Rini * 487694558STom Rini * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 587694558STom Rini * 687694558STom Rini * SPDX-License-Identifier: GPL-2.0+ 787694558STom Rini * 887694558STom Rini * The various ARMv7 SoCs from TI all share a number of IP blocks when 987694558STom Rini * implementing a given feature. Rather than define these in every 1087694558STom Rini * board or even SoC common file, we define a common file to be re-used 1187694558STom Rini * in all cases. While technically true that some of these details are 1287694558STom Rini * configurable at the board design, they are common throughout SoC 1387694558STom Rini * reference platforms as well as custom designs and become de facto 1487694558STom Rini * standards. 1587694558STom Rini */ 1687694558STom Rini 1787694558STom Rini #ifndef __CONFIG_TI_ARMV7_COMMON_H__ 1887694558STom Rini #define __CONFIG_TI_ARMV7_COMMON_H__ 1987694558STom Rini 2087694558STom Rini /* Common define for many platforms. */ 2187694558STom Rini #define CONFIG_OMAP 2287694558STom Rini #define CONFIG_OMAP_COMMON 230dd54619STom Rini #define CONFIG_SYS_GENERIC_BOARD 2487694558STom Rini 2587694558STom Rini /* 2687694558STom Rini * We typically do not contain NOR flash. In the cases where we do, we 2787694558STom Rini * undefine this later. 2887694558STom Rini */ 2987694558STom Rini #define CONFIG_SYS_NO_FLASH 3087694558STom Rini 3187694558STom Rini /* Support both device trees and ATAGs. */ 3287694558STom Rini #define CONFIG_OF_LIBFDT 3387694558STom Rini #define CONFIG_CMDLINE_TAG 3487694558STom Rini #define CONFIG_SETUP_MEMORY_TAGS 3587694558STom Rini #define CONFIG_INITRD_TAG 3687694558STom Rini 3787694558STom Rini /* 3887694558STom Rini * Our DDR memory always starts at 0x80000000 and U-Boot shall have 3987694558STom Rini * relocated itself to higher in memory by the time this value is used. 40fb3ad9bdSTom Rini * However, set this to a 32MB offset to allow for easier Linux kernel 41fb3ad9bdSTom Rini * booting as the default is often used as the kernel load address. 4287694558STom Rini */ 43fb3ad9bdSTom Rini #define CONFIG_SYS_LOAD_ADDR 0x82000000 44fb3ad9bdSTom Rini 45fb3ad9bdSTom Rini /* 46fb3ad9bdSTom Rini * We setup defaults based on constraints from the Linux kernel, which should 47fb3ad9bdSTom Rini * also be safe elsewhere. We have the default load at 32MB into DDR (for 48fb3ad9bdSTom Rini * the kernel), FDT above 128MB (the maximum location for the end of the 49fb3ad9bdSTom Rini * kernel), and the ramdisk 512KB above that (allowing for hopefully never 50fb3ad9bdSTom Rini * seen large trees). We say all of this must be within the first 256MB 51fb3ad9bdSTom Rini * as that will normally be within the kernel lowmem and thus visible via 52fb3ad9bdSTom Rini * bootm_size and we only run on platforms with 256MB or more of memory. 53fb3ad9bdSTom Rini */ 54fb3ad9bdSTom Rini #define DEFAULT_LINUX_BOOT_ENV \ 55fb3ad9bdSTom Rini "loadaddr=0x82000000\0" \ 56fb3ad9bdSTom Rini "kernel_addr_r=0x82000000\0" \ 57fb3ad9bdSTom Rini "fdtaddr=0x88000000\0" \ 58fb3ad9bdSTom Rini "fdt_addr_r=0x88000000\0" \ 59fb3ad9bdSTom Rini "rdaddr=0x88080000\0" \ 60fb3ad9bdSTom Rini "ramdisk_addr_r=0x88080000\0" \ 61fb3ad9bdSTom Rini "bootm_size=0x10000000\0" 6287694558STom Rini 6387694558STom Rini /* 6487694558STom Rini * Default to a quick boot delay. 6587694558STom Rini */ 6687694558STom Rini #define CONFIG_BOOTDELAY 1 6787694558STom Rini 6887694558STom Rini /* 69c6a7fce1SEnric Balletbò i Serra * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, 70c6a7fce1SEnric Balletbò i Serra * we say (for simplicity) that we have 1 bank, always, even when 71c6a7fce1SEnric Balletbò i Serra * we have more. We always start at 0x80000000, and we place the 72c6a7fce1SEnric Balletbò i Serra * initial stack pointer in our SRAM. Otherwise, we can define 73c6a7fce1SEnric Balletbò i Serra * CONFIG_NR_DRAM_BANKS before including this file. 7487694558STom Rini */ 75c6a7fce1SEnric Balletbò i Serra #ifndef CONFIG_NR_DRAM_BANKS 7687694558STom Rini #define CONFIG_NR_DRAM_BANKS 1 77c6a7fce1SEnric Balletbò i Serra #endif 7887694558STom Rini #define CONFIG_SYS_SDRAM_BASE 0x80000000 7987694558STom Rini #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 8087694558STom Rini GENERATED_GBL_DATA_SIZE) 8187694558STom Rini 8287694558STom Rini /* Timer information. */ 8387694558STom Rini #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 8487694558STom Rini 8587694558STom Rini /* I2C IP block */ 8687694558STom Rini #define CONFIG_I2C 871dd44e5aSTom Rini #define CONFIG_CMD_I2C 886789e84eSHeiko Schocher #define CONFIG_SYS_I2C 896789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 906789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 916789e84eSHeiko Schocher #define CONFIG_SYS_I2C_OMAP24XX 9287694558STom Rini 9387694558STom Rini /* MMC/SD IP block */ 9487694558STom Rini #define CONFIG_MMC 9587694558STom Rini #define CONFIG_GENERIC_MMC 9687694558STom Rini #define CONFIG_OMAP_HSMMC 9787694558STom Rini #define CONFIG_CMD_MMC 9887694558STom Rini 9987694558STom Rini /* McSPI IP block */ 10087694558STom Rini #define CONFIG_SPI 10187694558STom Rini #define CONFIG_OMAP3_SPI 1020fedc4a5STom Rini #define CONFIG_CMD_SPI 10387694558STom Rini 10487694558STom Rini /* GPIO block */ 10587694558STom Rini #define CONFIG_OMAP_GPIO 106a1665ed1STom Rini #define CONFIG_CMD_GPIO 10787694558STom Rini 10887694558STom Rini /* 10987694558STom Rini * GPMC NAND block. We support 1 device and the physical address to 11087694558STom Rini * access CS0 at is 0x8000000. 11187694558STom Rini */ 11287694558STom Rini #ifdef CONFIG_NAND 11387694558STom Rini #define CONFIG_NAND_OMAP_GPMC 114df4dbb5dSTom Rini #ifndef CONFIG_SYS_NAND_BASE 11587694558STom Rini #define CONFIG_SYS_NAND_BASE 0x8000000 116df4dbb5dSTom Rini #endif 11787694558STom Rini #define CONFIG_SYS_MAX_NAND_DEVICE 1 1181dd44e5aSTom Rini #define CONFIG_CMD_NAND 11987694558STom Rini #endif 12087694558STom Rini 12187694558STom Rini /* 12287694558STom Rini * The following are general good-enough settings for U-Boot. We set a 12387694558STom Rini * large malloc pool as we generally have a lot of DDR, and we opt for 12487694558STom Rini * function over binary size in the main portion of U-Boot as this is 12587694558STom Rini * generally easily constrained later if needed. We enable the config 12687694558STom Rini * options that give us information in the environment about what board 12787694558STom Rini * we are on so we do not need to rely on the command prompt. We set a 12887694558STom Rini * console baudrate of 115200 and use the default baud rate table. 12987694558STom Rini */ 1300e1612a7SSimon Glass #define CONFIG_SYS_MALLOC_LEN (16 << 20) 13187694558STom Rini #define CONFIG_SYS_HUSH_PARSER 1321dd44e5aSTom Rini #define CONFIG_SYS_PROMPT "U-Boot# " 1331dd44e5aSTom Rini #define CONFIG_SYS_CONSOLE_INFO_QUIET 1341dd44e5aSTom Rini #define CONFIG_BAUDRATE 115200 1351dd44e5aSTom Rini #define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ 1361dd44e5aSTom Rini #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ 1371dd44e5aSTom Rini 1381dd44e5aSTom Rini /* As stated above, the following choices are optional. */ 1391dd44e5aSTom Rini #define CONFIG_SYS_LONGHELP 14087694558STom Rini #define CONFIG_AUTO_COMPLETE 14187694558STom Rini #define CONFIG_CMDLINE_EDITING 14287694558STom Rini #define CONFIG_VERSION_VARIABLE 14387694558STom Rini 14487694558STom Rini /* We set the max number of command args high to avoid HUSH bugs. */ 14587694558STom Rini #define CONFIG_SYS_MAXARGS 64 14687694558STom Rini 14787694558STom Rini /* Console I/O Buffer Size */ 14887694558STom Rini #define CONFIG_SYS_CBSIZE 512 14987694558STom Rini /* Print Buffer Size */ 15087694558STom Rini #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 15187694558STom Rini + sizeof(CONFIG_SYS_PROMPT) + 16) 15287694558STom Rini /* Boot Argument Buffer Size */ 15387694558STom Rini #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 15487694558STom Rini 15587694558STom Rini /* 15687694558STom Rini * When we have SPI, NOR or NAND flash we expect to be making use of 15787694558STom Rini * mtdparts, both for ease of use in U-Boot and for passing information 15887694558STom Rini * on to the Linux kernel. 15987694558STom Rini */ 16087694558STom Rini #if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) 16187694558STom Rini #define CONFIG_MTD_DEVICE /* Required for mtdparts */ 16287694558STom Rini #define CONFIG_CMD_MTDPARTS 16387694558STom Rini #endif 16487694558STom Rini 16587694558STom Rini /* 16687694558STom Rini * For commands to use, we take the default list and add a few other 16787694558STom Rini * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH 16887694558STom Rini * prior to this include, in order to skip a few commands. When we do 16987694558STom Rini * have flash, if we expect these commands they must be enabled in that 1701dd44e5aSTom Rini * config. If desired, a specific list of desired commands can be used 1711dd44e5aSTom Rini * instead. 17287694558STom Rini */ 17387694558STom Rini #include <config_cmd_default.h> 17487694558STom Rini #define CONFIG_CMD_ASKENV 17587694558STom Rini #define CONFIG_CMD_ECHO 17687694558STom Rini #define CONFIG_CMD_BOOTZ 1776440b807SGuillaume GARDET #define CONFIG_SUPPORT_RAW_INITRD 17887694558STom Rini 17987694558STom Rini /* 18087694558STom Rini * Common filesystems support. When we have removable storage we 18187694558STom Rini * enabled a number of useful commands and support. 18287694558STom Rini */ 18387694558STom Rini #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) 18487694558STom Rini #define CONFIG_DOS_PARTITION 18587694558STom Rini #define CONFIG_CMD_FAT 18687694558STom Rini #define CONFIG_FAT_WRITE 18787694558STom Rini #define CONFIG_CMD_EXT2 18887694558STom Rini #define CONFIG_CMD_EXT4 18987694558STom Rini #define CONFIG_CMD_FS_GENERIC 19087694558STom Rini #endif 19187694558STom Rini 19287694558STom Rini /* 19387694558STom Rini * Our platforms make use of SPL to initalize the hardware (primarily 19487694558STom Rini * memory) enough for full U-Boot to be loaded. We also support Falcon 19587694558STom Rini * Mode so that the Linux kernel can be booted directly from SPL 19687694558STom Rini * instead, if desired. We make use of the general SPL framework found 19787694558STom Rini * under common/spl/. Given our generally common memory map, we set a 19887694558STom Rini * number of related defaults and sizes here. 19987694558STom Rini */ 2007a5f71bcSSourav Poddar #if !defined(CONFIG_NOR_BOOT) && \ 2017a5f71bcSSourav Poddar !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) 20287694558STom Rini #define CONFIG_SPL_FRAMEWORK 20387694558STom Rini #define CONFIG_SPL_OS_BOOT 20487694558STom Rini 20587694558STom Rini /* 206865813edSTom Rini * Place the image at the start of the ROM defined image space (per 207865813edSTom Rini * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined 208865813edSTom Rini * downloaded image area. We initalize DRAM as soon as we can so that 209865813edSTom Rini * we can place stack, malloc and BSS there. We load U-Boot itself into 210865813edSTom Rini * memory at 0x80800000 for legacy reasons (to not conflict with older 211865813edSTom Rini * SPLs). We have our BSS be placed 2MiB after this, to allow for the 212865813edSTom Rini * default Linux kernel address of 0x80008000 to work with most sized 213865813edSTom Rini * kernels, in the Falcon Mode case. We have the SPL malloc pool at the 214865813edSTom Rini * end of the BSS area. We place our stack at 32MiB after the start of 215865813edSTom Rini * DRAM to allow room for all of the above. 21687694558STom Rini */ 217865813edSTom Rini #define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) 218df4dbb5dSTom Rini #ifndef CONFIG_SYS_TEXT_BASE 21987694558STom Rini #define CONFIG_SYS_TEXT_BASE 0x80800000 220df4dbb5dSTom Rini #endif 221df4dbb5dSTom Rini #ifndef CONFIG_SPL_BSS_START_ADDR 22287694558STom Rini #define CONFIG_SPL_BSS_START_ADDR 0x80a00000 22387694558STom Rini #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 224df4dbb5dSTom Rini #endif 225df4dbb5dSTom Rini #ifndef CONFIG_SYS_SPL_MALLOC_START 22687694558STom Rini #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 22787694558STom Rini CONFIG_SPL_BSS_MAX_SIZE) 22887694558STom Rini #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 229df4dbb5dSTom Rini #endif 23087694558STom Rini 23187694558STom Rini /* RAW SD card / eMMC locations. */ 23287694558STom Rini #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 23387694558STom Rini #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 23487694558STom Rini 23587694558STom Rini /* FAT sd card locations. */ 236*e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 237205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 23887694558STom Rini 23987694558STom Rini #ifdef CONFIG_SPL_OS_BOOT 24087694558STom Rini /* FAT */ 241205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 242205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 24387694558STom Rini 24487694558STom Rini /* RAW SD card / eMMC */ 24587694558STom Rini #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 24687694558STom Rini #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 24787694558STom Rini #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 24887694558STom Rini 24987694558STom Rini /* spl export command */ 25087694558STom Rini #define CONFIG_CMD_SPL 25187694558STom Rini #endif 25287694558STom Rini 25387694558STom Rini #ifdef CONFIG_MMC 254a7142dd0STom Rini #define CONFIG_SPL_LIBDISK_SUPPORT 25587694558STom Rini #define CONFIG_SPL_MMC_SUPPORT 25687694558STom Rini #define CONFIG_SPL_FAT_SUPPORT 25787694558STom Rini #endif 25887694558STom Rini 259a7142dd0STom Rini /* General parts of the framework, required. */ 26087694558STom Rini #define CONFIG_SPL_I2C_SUPPORT 26187694558STom Rini #define CONFIG_SPL_LIBCOMMON_SUPPORT 26287694558STom Rini #define CONFIG_SPL_LIBGENERIC_SUPPORT 26387694558STom Rini #define CONFIG_SPL_SERIAL_SUPPORT 26487694558STom Rini #define CONFIG_SPL_GPIO_SUPPORT 26587694558STom Rini #define CONFIG_SPL_BOARD_INIT 26687694558STom Rini 26787694558STom Rini #ifdef CONFIG_NAND 26887694558STom Rini #define CONFIG_SPL_NAND_SUPPORT 26987694558STom Rini #define CONFIG_SPL_NAND_BASE 27087694558STom Rini #define CONFIG_SPL_NAND_DRIVERS 27187694558STom Rini #define CONFIG_SPL_NAND_ECC 2726dd3b566STom Rini #define CONFIG_SPL_MTD_SUPPORT 27387694558STom Rini #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 27487694558STom Rini #endif 27587694558STom Rini #endif /* !CONFIG_NOR_BOOT */ 27687694558STom Rini 27787694558STom Rini #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ 278