1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ti816x_evm.h 4 * 5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 6 * Antoine Tenart, <atenart@adeneo-embedded.com> 7 */ 8 9 #ifndef __CONFIG_TI816X_EVM_H 10 #define __CONFIG_TI816X_EVM_H 11 12 #include <configs/ti_armv7_omap.h> 13 #include <asm/arch/omap.h> 14 15 #define CONFIG_ENV_SIZE 0x2000 16 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM 17 18 #define CONFIG_EXTRA_ENV_SETTINGS \ 19 DEFAULT_LINUX_BOOT_ENV \ 20 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 21 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 22 23 #define CONFIG_BOOTCOMMAND \ 24 "mmc rescan;" \ 25 "fatload mmc 0 ${loadaddr} uImage;" \ 26 "bootm ${loadaddr}" \ 27 28 /* Clock Defines */ 29 #define V_OSCK 24000000 /* Clock output from T2 */ 30 #define V_SCLK (V_OSCK >> 1) 31 32 #define CONFIG_CMD_ASKENV 33 34 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 35 #define CONFIG_SYS_SDRAM_BASE 0x80000000 36 37 /** 38 * Platform/Board specific defs 39 */ 40 #define CONFIG_SYS_CLK_FREQ 27000000 41 #define CONFIG_SYS_TIMERBASE 0x4802E000 42 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 43 44 /* 45 * NS16550 Configuration 46 */ 47 #define CONFIG_SYS_NS16550_SERIAL 48 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 49 #define CONFIG_SYS_NS16550_CLK (48000000) 50 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 51 52 /* allow overwriting serial config and ethaddr */ 53 #define CONFIG_ENV_OVERWRITE 54 55 56 /* 57 * GPMC NAND block. We support 1 device and the physical address to 58 * access CS0 at is 0x8000000. 59 */ 60 #define CONFIG_SYS_NAND_BASE 0x8000000 61 #define CONFIG_SYS_MAX_NAND_DEVICE 1 62 63 /* NAND: SPL related configs */ 64 65 /* NAND: device related configs */ 66 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 67 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 68 CONFIG_SYS_NAND_PAGE_SIZE) 69 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 70 #define CONFIG_SYS_NAND_OOBSIZE 64 71 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 72 /* NAND: driver related configs */ 73 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 74 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 75 10, 11, 12, 13, 14, 15, 16, 17, \ 76 18, 19, 20, 21, 22, 23, 24, 25, \ 77 26, 27, 28, 29, 30, 31, 32, 33, \ 78 34, 35, 36, 37, 38, 39, 40, 41, \ 79 42, 43, 44, 45, 46, 47, 48, 49, \ 80 50, 51, 52, 53, 54, 55, 56, 57, } 81 82 #define CONFIG_SYS_NAND_ECCSIZE 512 83 #define CONFIG_SYS_NAND_ECCBYTES 14 84 #define CONFIG_SYS_NAND_ONFI_DETECTION 85 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 86 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 87 #define CONFIG_ENV_OFFSET 0x001c0000 88 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 89 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 90 91 /* SPL */ 92 /* Defines for SPL */ 93 #define CONFIG_SPL_TEXT_BASE 0x40400000 94 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 95 CONFIG_SPL_TEXT_BASE) 96 97 #define CONFIG_BOOTP_DNS2 98 #define CONFIG_BOOTP_SEND_HOSTNAME 99 #define CONFIG_NET_RETRY_COUNT 10 100 101 /* Since SPL did pll and ddr initialization for us, 102 * we don't need to do it twice. 103 */ 104 #ifndef CONFIG_SPL_BUILD 105 #define CONFIG_SKIP_LOWLEVEL_INIT 106 #endif 107 108 /* 109 * Disable MMC DM for SPL build and can be re-enabled after adding 110 * DM support in SPL 111 */ 112 #ifdef CONFIG_SPL_BUILD 113 #undef CONFIG_DM_MMC 114 #undef CONFIG_TIMER 115 #endif 116 #endif 117