xref: /openbmc/u-boot/include/configs/ti816x_evm.h (revision 3788b451)
1 /*
2  * ti816x_evm.h
3  *
4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5  * Antoine Tenart, <atenart@adeneo-embedded.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_TI816X_EVM_H
11 #define __CONFIG_TI816X_EVM_H
12 
13 #define CONFIG_TI81XX
14 #define CONFIG_TI816X
15 #define CONFIG_SYS_NO_FLASH
16 #define CONFIG_OMAP
17 
18 #define CONFIG_ARCH_CPU_INIT
19 
20 #include <asm/arch/omap.h>
21 
22 #define CONFIG_ENV_SIZE			0x2000
23 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (32 * 1024))
24 #define CONFIG_SYS_LONGHELP		/* undef save memory */
25 #define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM
26 
27 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
28 #define CONFIG_SETUP_MEMORY_TAGS
29 #define CONFIG_INITRD_TAG		/* required for ramdisk support */
30 
31 #define CONFIG_EXTRA_ENV_SETTINGS	\
32 	"loadaddr=0x81000000\0"		\
33 
34 #define CONFIG_BOOTCOMMAND			\
35 	"mmc rescan;"				\
36 	"fatload mmc 0 ${loadaddr} uImage;"	\
37 	"bootm ${loadaddr}"			\
38 
39 #define CONFIG_BOOTARGS	"console=ttyO2,115200n8 noinitrd earlyprintk"
40 
41 /* Clock Defines */
42 #define V_OSCK          24000000    /* Clock output from T2 */
43 #define V_SCLK          (V_OSCK >> 1)
44 
45 #define CONFIG_SYS_MAXARGS	32
46 #define CONFIG_SYS_CBSIZE	512 /* console I/O buffer size */
47 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
48 		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
49 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* boot arg buffer size */
50 
51 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
52 
53 #define CONFIG_CMD_ASKEN
54 #define CONFIG_OMAP_GPIO
55 #define CONFIG_GENERIC_MMC
56 #define CONFIG_DOS_PARTITION
57 
58 #define CONFIG_FS_FAT
59 
60 /*
61  * Only one of the following two options (DDR3/DDR2) should be enabled
62  * CONFIG_TI816X_EVM_DDR2
63  * CONFIG_TI816X_EVM_DDR3
64  */
65 #define CONFIG_TI816X_EVM_DDR3
66 
67 /*
68  * Supported values: 400, 531, 675 or 796 MHz
69  */
70 #define CONFIG_TI816X_DDR_PLL_796
71 
72 #define CONFIG_TI816X_USE_EMIF0	1
73 #define CONFIG_TI816X_USE_EMIF1	1
74 
75 #define CONFIG_NR_DRAM_BANKS	2		/* we have 2 banks of DRAM */
76 #define PHYS_DRAM_1		0x80000000	/* DRAM Bank #1 */
77 #define PHYS_DRAM_1_SIZE        0x40000000	/* 1 GB */
78 #define PHYS_DRAM_2		0xC0000000	/* DRAM Bank #2 */
79 #define PHYS_DRAM_2_SIZE	0x40000000	/* 1 GB */
80 
81 #define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
82 #define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
83 #define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
84 		GENERATED_GBL_DATA_SIZE)
85 
86 /**
87  * Platform/Board specific defs
88  */
89 #define CONFIG_SYS_CLK_FREQ     27000000
90 #define CONFIG_SYS_TIMERBASE    0x4802E000
91 #define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
92 
93 #undef CONFIG_NAND_OMAP_GPMC
94 
95 /*
96  * NS16550 Configuration
97  */
98 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
100 #define CONFIG_SYS_NS16550_CLK      (48000000)
101 #define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
102 
103 #define CONFIG_BAUDRATE     115200
104 
105 /* allow overwriting serial config and ethaddr */
106 #define CONFIG_ENV_OVERWRITE
107 
108 #define CONFIG_SERIAL1
109 #define CONFIG_SERIAL2
110 #define CONFIG_SERIAL3
111 #define CONFIG_CONS_INDEX	1
112 
113 #define CONFIG_ENV_IS_NOWHERE
114 
115 /* SPL */
116 /* Defines for SPL */
117 #define CONFIG_SPL_FRAMEWORK
118 #define CONFIG_SPL_TEXT_BASE    0x40400000
119 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
120 					 CONFIG_SPL_TEXT_BASE)
121 
122 #define CONFIG_SPL_BSS_START_ADDR   0x80000000
123 #define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */
124 
125 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
126 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
127 
128 #define CONFIG_SYS_SPI_U_BOOT_OFFS  0x20000
129 #define CONFIG_SYS_SPI_U_BOOT_SIZE  0x40000
130 #define CONFIG_SPL_LDSCRIPT     "arch/arm/mach-omap2/u-boot-spl.lds"
131 
132 #define CONFIG_SPL_BOARD_INIT
133 
134 #define CONFIG_SYS_TEXT_BASE        0x80800000
135 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
136 #define CONFIG_SYS_SPL_MALLOC_SIZE  0x100000
137 
138 /* Since SPL did pll and ddr initialization for us,
139  * we don't need to do it twice.
140  */
141 #ifndef CONFIG_SPL_BUILD
142 #define CONFIG_SKIP_LOWLEVEL_INIT
143 #endif
144 
145 /* Unsupported features */
146 #undef CONFIG_USE_IRQ
147 
148 #endif
149