1 /** 2 * (C) Copyright 2014, Cavium Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 **/ 6 7 #ifndef __THUNDERX_88XX_H__ 8 #define __THUNDERX_88XX_H__ 9 10 #define CONFIG_REMAKE_ELF 11 12 #define CONFIG_THUNDERX 13 14 #define CONFIG_SYS_64BIT 15 16 #define CONFIG_SYS_NO_FLASH 17 18 19 #define CONFIG_IDENT_STRING \ 20 " for Cavium Thunder CN88XX ARM v8 Multi-Core" 21 #define CONFIG_BOOTP_VCI_STRING "Diagnostics" 22 23 #define MEM_BASE 0x00500000 24 25 #define CONFIG_COREID_MASK 0xffffff 26 27 #define CONFIG_SYS_FULL_VA 28 29 #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ 30 PTL2_MEMTYPE(MT_NORMAL) | \ 31 PTL2_BLOCK_NON_SHARE}, \ 32 {0x800000000000UL, 0x40000000000UL, \ 33 PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 34 PTL2_BLOCK_NON_SHARE}, \ 35 {0x840000000000UL, 0x40000000000UL, \ 36 PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 37 PTL2_BLOCK_NON_SHARE}, \ 38 } 39 40 #define CONFIG_SYS_MEM_MAP_SIZE 3 41 42 #define CONFIG_SYS_VA_BITS 48 43 #define CONFIG_SYS_PTL2_BITS 42 44 #define CONFIG_SYS_BLOCK_SHIFT 29 45 #define CONFIG_SYS_PTL1_ENTRIES 64 46 #define CONFIG_SYS_PTL2_ENTRIES 8192 47 48 #define CONFIG_SYS_PGTABLE_SIZE \ 49 ((CONFIG_SYS_PTL1_ENTRIES + \ 50 CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) 51 #define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) 52 #define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) 53 #define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) 54 55 /* Link Definitions */ 56 #define CONFIG_SYS_TEXT_BASE 0x00500000 57 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 58 59 /* Flat Device Tree Definitions */ 60 #define CONFIG_OF_LIBFDT 61 62 /* SMP Spin Table Definitions */ 63 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 64 65 66 /* Generic Timer Definitions */ 67 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 68 69 70 #define CONFIG_SYS_MEMTEST_START MEM_BASE 71 #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 72 73 /* Size of malloc() pool */ 74 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 75 76 /* PL011 Serial Configuration */ 77 78 #define CONFIG_PL01X_SERIAL 79 #define CONFIG_PL011_CLOCK 24000000 80 #define CONFIG_CONS_INDEX 1 81 82 /* Generic Interrupt Controller Definitions */ 83 #define GICD_BASE (0x801000000000) 84 #define GICR_BASE (0x801000002000) 85 #define CONFIG_SYS_SERIAL0 0x87e024000000 86 #define CONFIG_SYS_SERIAL1 0x87e025000000 87 88 #define CONFIG_BAUDRATE 115200 89 90 /* Command line configuration */ 91 #define CONFIG_MENU 92 93 /* BOOTP options */ 94 #define CONFIG_BOOTP_BOOTFILESIZE 95 #define CONFIG_BOOTP_BOOTPATH 96 #define CONFIG_BOOTP_GATEWAY 97 #define CONFIG_BOOTP_HOSTNAME 98 #define CONFIG_BOOTP_PXE 99 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 100 101 /* Miscellaneous configurable options */ 102 #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 103 104 /* Physical Memory Map */ 105 #define CONFIG_NR_DRAM_BANKS 1 106 #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 107 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 108 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 109 110 /* Initial environment variables */ 111 #define UBOOT_IMG_HEAD_SIZE 0x40 112 /* C80000 - 0x40 */ 113 #define CONFIG_EXTRA_ENV_SETTINGS \ 114 "kernel_addr=08007ffc0\0" \ 115 "fdt_addr=0x94C00000\0" \ 116 "fdt_high=0x9fffffff\0" 117 118 #define CONFIG_BOOTARGS \ 119 "console=ttyAMA0,115200n8 " \ 120 "earlycon=pl011,0x87e024000000 " \ 121 "debug maxcpus=48 rootwait rw "\ 122 "root=/dev/sda2 coherent_pool=16M" 123 #define CONFIG_BOOTDELAY 5 124 125 /* Do not preserve environment */ 126 #define CONFIG_ENV_IS_NOWHERE 1 127 #define CONFIG_ENV_SIZE 0x1000 128 129 /* Monitor Command Prompt */ 130 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 132 sizeof(CONFIG_SYS_PROMPT) + 16) 133 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 135 #define CONFIG_SYS_LONGHELP 136 #define CONFIG_CMDLINE_EDITING 1 137 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 138 #define CONFIG_NO_RELOCATION 1 139 #define CONFIG_LIB_RAND 140 #define PLL_REF_CLK 50000000 /* 50 MHz */ 141 #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 142 143 #endif /* __THUNDERX_88XX_H__ */ 144