1 /** 2 * (C) Copyright 2014, Cavium Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 **/ 6 7 #ifndef __THUNDERX_88XX_H__ 8 #define __THUNDERX_88XX_H__ 9 10 #define CONFIG_REMAKE_ELF 11 12 #define CONFIG_THUNDERX 13 14 #define CONFIG_SYS_64BIT 15 16 #define CONFIG_SYS_NO_FLASH 17 18 19 #define CONFIG_IDENT_STRING \ 20 " for Cavium Thunder CN88XX ARM v8 Multi-Core" 21 #define CONFIG_BOOTP_VCI_STRING "Diagnostics" 22 23 #define MEM_BASE 0x00500000 24 25 #define CONFIG_SYS_FULL_VA 26 27 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE 28 29 #define CONFIG_SYS_MEM_MAP_SIZE 3 30 31 #define CONFIG_SYS_VA_BITS 48 32 #define CONFIG_SYS_PTL2_BITS 42 33 #define CONFIG_SYS_BLOCK_SHIFT 29 34 #define CONFIG_SYS_PTL1_ENTRIES 64 35 #define CONFIG_SYS_PTL2_ENTRIES 8192 36 37 #define CONFIG_SYS_PGTABLE_SIZE \ 38 ((CONFIG_SYS_PTL1_ENTRIES + \ 39 CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) 40 41 /* Link Definitions */ 42 #define CONFIG_SYS_TEXT_BASE 0x00500000 43 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 44 45 /* SMP Spin Table Definitions */ 46 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 47 48 49 /* Generic Timer Definitions */ 50 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 51 52 53 #define CONFIG_SYS_MEMTEST_START MEM_BASE 54 #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 55 56 /* Size of malloc() pool */ 57 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 58 59 /* PL011 Serial Configuration */ 60 61 #define CONFIG_PL01X_SERIAL 62 #define CONFIG_PL011_CLOCK 24000000 63 #define CONFIG_CONS_INDEX 1 64 65 /* Generic Interrupt Controller Definitions */ 66 #define GICD_BASE (0x801000000000) 67 #define GICR_BASE (0x801000002000) 68 #define CONFIG_SYS_SERIAL0 0x87e024000000 69 #define CONFIG_SYS_SERIAL1 0x87e025000000 70 71 #define CONFIG_BAUDRATE 115200 72 73 /* Command line configuration */ 74 #define CONFIG_MENU 75 76 /* BOOTP options */ 77 #define CONFIG_BOOTP_BOOTFILESIZE 78 #define CONFIG_BOOTP_BOOTPATH 79 #define CONFIG_BOOTP_GATEWAY 80 #define CONFIG_BOOTP_HOSTNAME 81 #define CONFIG_BOOTP_PXE 82 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 83 84 /* Miscellaneous configurable options */ 85 #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 86 87 /* Physical Memory Map */ 88 #define CONFIG_NR_DRAM_BANKS 1 89 #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 90 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 91 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 92 93 /* Initial environment variables */ 94 #define UBOOT_IMG_HEAD_SIZE 0x40 95 /* C80000 - 0x40 */ 96 #define CONFIG_EXTRA_ENV_SETTINGS \ 97 "kernel_addr=08007ffc0\0" \ 98 "fdt_addr=0x94C00000\0" \ 99 "fdt_high=0x9fffffff\0" 100 101 #define CONFIG_BOOTARGS \ 102 "console=ttyAMA0,115200n8 " \ 103 "earlycon=pl011,0x87e024000000 " \ 104 "debug maxcpus=48 rootwait rw "\ 105 "root=/dev/sda2 coherent_pool=16M" 106 #define CONFIG_BOOTDELAY 5 107 108 /* Do not preserve environment */ 109 #define CONFIG_ENV_IS_NOWHERE 1 110 #define CONFIG_ENV_SIZE 0x1000 111 112 /* Monitor Command Prompt */ 113 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 115 sizeof(CONFIG_SYS_PROMPT) + 16) 116 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 118 #define CONFIG_SYS_LONGHELP 119 #define CONFIG_CMDLINE_EDITING 1 120 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 121 #define CONFIG_NO_RELOCATION 1 122 #define CONFIG_LIB_RAND 123 #define PLL_REF_CLK 50000000 /* 50 MHz */ 124 #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 125 126 #endif /* __THUNDERX_88XX_H__ */ 127