1 /** 2 * (C) Copyright 2014, Cavium Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 **/ 6 7 #ifndef __THUNDERX_88XX_H__ 8 #define __THUNDERX_88XX_H__ 9 10 #define CONFIG_REMAKE_ELF 11 12 #define CONFIG_THUNDERX 13 14 #define CONFIG_SYS_64BIT 15 16 #define CONFIG_SYS_NO_FLASH 17 18 19 #define CONFIG_IDENT_STRING \ 20 " for Cavium Thunder CN88XX ARM v8 Multi-Core" 21 #define CONFIG_BOOTP_VCI_STRING "Diagnostics" 22 23 #define MEM_BASE 0x00500000 24 25 #define CONFIG_COREID_MASK 0xffffff 26 27 #define CONFIG_SYS_FULL_VA 28 29 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE 30 31 #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ 32 PTL2_MEMTYPE(MT_NORMAL) | \ 33 PTL2_BLOCK_NON_SHARE}, \ 34 {0x800000000000UL, 0x40000000000UL, \ 35 PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 36 PTL2_BLOCK_NON_SHARE}, \ 37 {0x840000000000UL, 0x40000000000UL, \ 38 PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 39 PTL2_BLOCK_NON_SHARE}, \ 40 } 41 42 #define CONFIG_SYS_MEM_MAP_SIZE 3 43 44 #define CONFIG_SYS_VA_BITS 48 45 #define CONFIG_SYS_PTL2_BITS 42 46 #define CONFIG_SYS_BLOCK_SHIFT 29 47 #define CONFIG_SYS_PTL1_ENTRIES 64 48 #define CONFIG_SYS_PTL2_ENTRIES 8192 49 50 #define CONFIG_SYS_PGTABLE_SIZE \ 51 ((CONFIG_SYS_PTL1_ENTRIES + \ 52 CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) 53 #define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) 54 #define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) 55 #define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) 56 57 /* Link Definitions */ 58 #define CONFIG_SYS_TEXT_BASE 0x00500000 59 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 60 61 /* Flat Device Tree Definitions */ 62 #define CONFIG_OF_LIBFDT 63 64 /* SMP Spin Table Definitions */ 65 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 66 67 68 /* Generic Timer Definitions */ 69 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 70 71 72 #define CONFIG_SYS_MEMTEST_START MEM_BASE 73 #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 74 75 /* Size of malloc() pool */ 76 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 77 78 /* PL011 Serial Configuration */ 79 80 #define CONFIG_PL01X_SERIAL 81 #define CONFIG_PL011_CLOCK 24000000 82 #define CONFIG_CONS_INDEX 1 83 84 /* Generic Interrupt Controller Definitions */ 85 #define GICD_BASE (0x801000000000) 86 #define GICR_BASE (0x801000002000) 87 #define CONFIG_SYS_SERIAL0 0x87e024000000 88 #define CONFIG_SYS_SERIAL1 0x87e025000000 89 90 #define CONFIG_BAUDRATE 115200 91 92 /* Command line configuration */ 93 #define CONFIG_MENU 94 95 /* BOOTP options */ 96 #define CONFIG_BOOTP_BOOTFILESIZE 97 #define CONFIG_BOOTP_BOOTPATH 98 #define CONFIG_BOOTP_GATEWAY 99 #define CONFIG_BOOTP_HOSTNAME 100 #define CONFIG_BOOTP_PXE 101 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 102 103 /* Miscellaneous configurable options */ 104 #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 105 106 /* Physical Memory Map */ 107 #define CONFIG_NR_DRAM_BANKS 1 108 #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 109 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 110 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 111 112 /* Initial environment variables */ 113 #define UBOOT_IMG_HEAD_SIZE 0x40 114 /* C80000 - 0x40 */ 115 #define CONFIG_EXTRA_ENV_SETTINGS \ 116 "kernel_addr=08007ffc0\0" \ 117 "fdt_addr=0x94C00000\0" \ 118 "fdt_high=0x9fffffff\0" 119 120 #define CONFIG_BOOTARGS \ 121 "console=ttyAMA0,115200n8 " \ 122 "earlycon=pl011,0x87e024000000 " \ 123 "debug maxcpus=48 rootwait rw "\ 124 "root=/dev/sda2 coherent_pool=16M" 125 #define CONFIG_BOOTDELAY 5 126 127 /* Do not preserve environment */ 128 #define CONFIG_ENV_IS_NOWHERE 1 129 #define CONFIG_ENV_SIZE 0x1000 130 131 /* Monitor Command Prompt */ 132 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 133 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 134 sizeof(CONFIG_SYS_PROMPT) + 16) 135 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 136 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 137 #define CONFIG_SYS_LONGHELP 138 #define CONFIG_CMDLINE_EDITING 1 139 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 140 #define CONFIG_NO_RELOCATION 1 141 #define CONFIG_LIB_RAND 142 #define PLL_REF_CLK 50000000 /* 50 MHz */ 143 #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 144 145 #endif /* __THUNDERX_88XX_H__ */ 146