1746f985aSSergey Temerkhanov /** 2746f985aSSergey Temerkhanov * (C) Copyright 2014, Cavium Inc. 3746f985aSSergey Temerkhanov * 4746f985aSSergey Temerkhanov * SPDX-License-Identifier: GPL-2.0+ 5746f985aSSergey Temerkhanov **/ 6746f985aSSergey Temerkhanov 7746f985aSSergey Temerkhanov #ifndef __THUNDERX_88XX_H__ 8746f985aSSergey Temerkhanov #define __THUNDERX_88XX_H__ 9746f985aSSergey Temerkhanov 10746f985aSSergey Temerkhanov #define CONFIG_REMAKE_ELF 11746f985aSSergey Temerkhanov 12746f985aSSergey Temerkhanov #define CONFIG_THUNDERX 13746f985aSSergey Temerkhanov 14746f985aSSergey Temerkhanov #define CONFIG_SYS_64BIT 15746f985aSSergey Temerkhanov 16746f985aSSergey Temerkhanov #define CONFIG_SYS_NO_FLASH 17746f985aSSergey Temerkhanov 18746f985aSSergey Temerkhanov 19746f985aSSergey Temerkhanov #define CONFIG_IDENT_STRING \ 20746f985aSSergey Temerkhanov " for Cavium Thunder CN88XX ARM v8 Multi-Core" 21746f985aSSergey Temerkhanov #define CONFIG_BOOTP_VCI_STRING "Diagnostics" 22746f985aSSergey Temerkhanov 23746f985aSSergey Temerkhanov #define MEM_BASE 0x00500000 24746f985aSSergey Temerkhanov 25746f985aSSergey Temerkhanov #define CONFIG_COREID_MASK 0xffffff 26746f985aSSergey Temerkhanov 27746f985aSSergey Temerkhanov #define CONFIG_SYS_FULL_VA 28746f985aSSergey Temerkhanov 29*900f88f3SSergey Temerkhanov #define CONFIG_SYS_LOWMEM_BASE MEM_BASE 30*900f88f3SSergey Temerkhanov 31746f985aSSergey Temerkhanov #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ 32746f985aSSergey Temerkhanov PTL2_MEMTYPE(MT_NORMAL) | \ 33746f985aSSergey Temerkhanov PTL2_BLOCK_NON_SHARE}, \ 34746f985aSSergey Temerkhanov {0x800000000000UL, 0x40000000000UL, \ 35746f985aSSergey Temerkhanov PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 36746f985aSSergey Temerkhanov PTL2_BLOCK_NON_SHARE}, \ 37746f985aSSergey Temerkhanov {0x840000000000UL, 0x40000000000UL, \ 38746f985aSSergey Temerkhanov PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 39746f985aSSergey Temerkhanov PTL2_BLOCK_NON_SHARE}, \ 40746f985aSSergey Temerkhanov } 41746f985aSSergey Temerkhanov 42746f985aSSergey Temerkhanov #define CONFIG_SYS_MEM_MAP_SIZE 3 43746f985aSSergey Temerkhanov 44746f985aSSergey Temerkhanov #define CONFIG_SYS_VA_BITS 48 45746f985aSSergey Temerkhanov #define CONFIG_SYS_PTL2_BITS 42 46746f985aSSergey Temerkhanov #define CONFIG_SYS_BLOCK_SHIFT 29 47746f985aSSergey Temerkhanov #define CONFIG_SYS_PTL1_ENTRIES 64 48746f985aSSergey Temerkhanov #define CONFIG_SYS_PTL2_ENTRIES 8192 49746f985aSSergey Temerkhanov 50746f985aSSergey Temerkhanov #define CONFIG_SYS_PGTABLE_SIZE \ 51746f985aSSergey Temerkhanov ((CONFIG_SYS_PTL1_ENTRIES + \ 52746f985aSSergey Temerkhanov CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) 53746f985aSSergey Temerkhanov #define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) 54746f985aSSergey Temerkhanov #define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) 55746f985aSSergey Temerkhanov #define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) 56746f985aSSergey Temerkhanov 57746f985aSSergey Temerkhanov /* Link Definitions */ 58746f985aSSergey Temerkhanov #define CONFIG_SYS_TEXT_BASE 0x00500000 59746f985aSSergey Temerkhanov #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 60746f985aSSergey Temerkhanov 61746f985aSSergey Temerkhanov /* Flat Device Tree Definitions */ 62746f985aSSergey Temerkhanov #define CONFIG_OF_LIBFDT 63746f985aSSergey Temerkhanov 64746f985aSSergey Temerkhanov /* SMP Spin Table Definitions */ 65746f985aSSergey Temerkhanov #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 66746f985aSSergey Temerkhanov 67746f985aSSergey Temerkhanov 68746f985aSSergey Temerkhanov /* Generic Timer Definitions */ 69746f985aSSergey Temerkhanov #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 70746f985aSSergey Temerkhanov 71746f985aSSergey Temerkhanov 72746f985aSSergey Temerkhanov #define CONFIG_SYS_MEMTEST_START MEM_BASE 73746f985aSSergey Temerkhanov #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 74746f985aSSergey Temerkhanov 75746f985aSSergey Temerkhanov /* Size of malloc() pool */ 76746f985aSSergey Temerkhanov #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 77746f985aSSergey Temerkhanov 78746f985aSSergey Temerkhanov /* PL011 Serial Configuration */ 79746f985aSSergey Temerkhanov 80746f985aSSergey Temerkhanov #define CONFIG_PL01X_SERIAL 81746f985aSSergey Temerkhanov #define CONFIG_PL011_CLOCK 24000000 82746f985aSSergey Temerkhanov #define CONFIG_CONS_INDEX 1 83746f985aSSergey Temerkhanov 84746f985aSSergey Temerkhanov /* Generic Interrupt Controller Definitions */ 85746f985aSSergey Temerkhanov #define GICD_BASE (0x801000000000) 86746f985aSSergey Temerkhanov #define GICR_BASE (0x801000002000) 87746f985aSSergey Temerkhanov #define CONFIG_SYS_SERIAL0 0x87e024000000 88746f985aSSergey Temerkhanov #define CONFIG_SYS_SERIAL1 0x87e025000000 89746f985aSSergey Temerkhanov 90746f985aSSergey Temerkhanov #define CONFIG_BAUDRATE 115200 91746f985aSSergey Temerkhanov 92746f985aSSergey Temerkhanov /* Command line configuration */ 93746f985aSSergey Temerkhanov #define CONFIG_MENU 94746f985aSSergey Temerkhanov 95746f985aSSergey Temerkhanov /* BOOTP options */ 96746f985aSSergey Temerkhanov #define CONFIG_BOOTP_BOOTFILESIZE 97746f985aSSergey Temerkhanov #define CONFIG_BOOTP_BOOTPATH 98746f985aSSergey Temerkhanov #define CONFIG_BOOTP_GATEWAY 99746f985aSSergey Temerkhanov #define CONFIG_BOOTP_HOSTNAME 100746f985aSSergey Temerkhanov #define CONFIG_BOOTP_PXE 101746f985aSSergey Temerkhanov #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 102746f985aSSergey Temerkhanov 103746f985aSSergey Temerkhanov /* Miscellaneous configurable options */ 104746f985aSSergey Temerkhanov #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 105746f985aSSergey Temerkhanov 106746f985aSSergey Temerkhanov /* Physical Memory Map */ 107746f985aSSergey Temerkhanov #define CONFIG_NR_DRAM_BANKS 1 108746f985aSSergey Temerkhanov #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 109746f985aSSergey Temerkhanov #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 110746f985aSSergey Temerkhanov #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 111746f985aSSergey Temerkhanov 112746f985aSSergey Temerkhanov /* Initial environment variables */ 113746f985aSSergey Temerkhanov #define UBOOT_IMG_HEAD_SIZE 0x40 114746f985aSSergey Temerkhanov /* C80000 - 0x40 */ 115746f985aSSergey Temerkhanov #define CONFIG_EXTRA_ENV_SETTINGS \ 116746f985aSSergey Temerkhanov "kernel_addr=08007ffc0\0" \ 117746f985aSSergey Temerkhanov "fdt_addr=0x94C00000\0" \ 118746f985aSSergey Temerkhanov "fdt_high=0x9fffffff\0" 119746f985aSSergey Temerkhanov 120746f985aSSergey Temerkhanov #define CONFIG_BOOTARGS \ 121746f985aSSergey Temerkhanov "console=ttyAMA0,115200n8 " \ 122746f985aSSergey Temerkhanov "earlycon=pl011,0x87e024000000 " \ 123746f985aSSergey Temerkhanov "debug maxcpus=48 rootwait rw "\ 124746f985aSSergey Temerkhanov "root=/dev/sda2 coherent_pool=16M" 125746f985aSSergey Temerkhanov #define CONFIG_BOOTDELAY 5 126746f985aSSergey Temerkhanov 127746f985aSSergey Temerkhanov /* Do not preserve environment */ 128746f985aSSergey Temerkhanov #define CONFIG_ENV_IS_NOWHERE 1 129746f985aSSergey Temerkhanov #define CONFIG_ENV_SIZE 0x1000 130746f985aSSergey Temerkhanov 131746f985aSSergey Temerkhanov /* Monitor Command Prompt */ 132746f985aSSergey Temerkhanov #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 133746f985aSSergey Temerkhanov #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 134746f985aSSergey Temerkhanov sizeof(CONFIG_SYS_PROMPT) + 16) 135746f985aSSergey Temerkhanov #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 136746f985aSSergey Temerkhanov #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 137746f985aSSergey Temerkhanov #define CONFIG_SYS_LONGHELP 138746f985aSSergey Temerkhanov #define CONFIG_CMDLINE_EDITING 1 139746f985aSSergey Temerkhanov #define CONFIG_SYS_MAXARGS 64 /* max command args */ 140746f985aSSergey Temerkhanov #define CONFIG_NO_RELOCATION 1 141746f985aSSergey Temerkhanov #define CONFIG_LIB_RAND 142746f985aSSergey Temerkhanov #define PLL_REF_CLK 50000000 /* 50 MHz */ 143746f985aSSergey Temerkhanov #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 144746f985aSSergey Temerkhanov 145746f985aSSergey Temerkhanov #endif /* __THUNDERX_88XX_H__ */ 146