1*746f985aSSergey Temerkhanov /** 2*746f985aSSergey Temerkhanov * (C) Copyright 2014, Cavium Inc. 3*746f985aSSergey Temerkhanov * 4*746f985aSSergey Temerkhanov * SPDX-License-Identifier: GPL-2.0+ 5*746f985aSSergey Temerkhanov **/ 6*746f985aSSergey Temerkhanov 7*746f985aSSergey Temerkhanov #ifndef __THUNDERX_88XX_H__ 8*746f985aSSergey Temerkhanov #define __THUNDERX_88XX_H__ 9*746f985aSSergey Temerkhanov 10*746f985aSSergey Temerkhanov #define CONFIG_REMAKE_ELF 11*746f985aSSergey Temerkhanov 12*746f985aSSergey Temerkhanov #define CONFIG_THUNDERX 13*746f985aSSergey Temerkhanov 14*746f985aSSergey Temerkhanov #define CONFIG_SYS_64BIT 15*746f985aSSergey Temerkhanov 16*746f985aSSergey Temerkhanov #define CONFIG_SYS_NO_FLASH 17*746f985aSSergey Temerkhanov 18*746f985aSSergey Temerkhanov 19*746f985aSSergey Temerkhanov #define CONFIG_IDENT_STRING \ 20*746f985aSSergey Temerkhanov " for Cavium Thunder CN88XX ARM v8 Multi-Core" 21*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_VCI_STRING "Diagnostics" 22*746f985aSSergey Temerkhanov 23*746f985aSSergey Temerkhanov #define MEM_BASE 0x00500000 24*746f985aSSergey Temerkhanov 25*746f985aSSergey Temerkhanov #define CONFIG_COREID_MASK 0xffffff 26*746f985aSSergey Temerkhanov 27*746f985aSSergey Temerkhanov #define CONFIG_SYS_FULL_VA 28*746f985aSSergey Temerkhanov 29*746f985aSSergey Temerkhanov #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ 30*746f985aSSergey Temerkhanov PTL2_MEMTYPE(MT_NORMAL) | \ 31*746f985aSSergey Temerkhanov PTL2_BLOCK_NON_SHARE}, \ 32*746f985aSSergey Temerkhanov {0x800000000000UL, 0x40000000000UL, \ 33*746f985aSSergey Temerkhanov PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 34*746f985aSSergey Temerkhanov PTL2_BLOCK_NON_SHARE}, \ 35*746f985aSSergey Temerkhanov {0x840000000000UL, 0x40000000000UL, \ 36*746f985aSSergey Temerkhanov PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ 37*746f985aSSergey Temerkhanov PTL2_BLOCK_NON_SHARE}, \ 38*746f985aSSergey Temerkhanov } 39*746f985aSSergey Temerkhanov 40*746f985aSSergey Temerkhanov #define CONFIG_SYS_MEM_MAP_SIZE 3 41*746f985aSSergey Temerkhanov 42*746f985aSSergey Temerkhanov #define CONFIG_SYS_VA_BITS 48 43*746f985aSSergey Temerkhanov #define CONFIG_SYS_PTL2_BITS 42 44*746f985aSSergey Temerkhanov #define CONFIG_SYS_BLOCK_SHIFT 29 45*746f985aSSergey Temerkhanov #define CONFIG_SYS_PTL1_ENTRIES 64 46*746f985aSSergey Temerkhanov #define CONFIG_SYS_PTL2_ENTRIES 8192 47*746f985aSSergey Temerkhanov 48*746f985aSSergey Temerkhanov #define CONFIG_SYS_PGTABLE_SIZE \ 49*746f985aSSergey Temerkhanov ((CONFIG_SYS_PTL1_ENTRIES + \ 50*746f985aSSergey Temerkhanov CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) 51*746f985aSSergey Temerkhanov #define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) 52*746f985aSSergey Temerkhanov #define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) 53*746f985aSSergey Temerkhanov #define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) 54*746f985aSSergey Temerkhanov 55*746f985aSSergey Temerkhanov /* Link Definitions */ 56*746f985aSSergey Temerkhanov #define CONFIG_SYS_TEXT_BASE 0x00500000 57*746f985aSSergey Temerkhanov #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 58*746f985aSSergey Temerkhanov 59*746f985aSSergey Temerkhanov /* Flat Device Tree Definitions */ 60*746f985aSSergey Temerkhanov #define CONFIG_OF_LIBFDT 61*746f985aSSergey Temerkhanov 62*746f985aSSergey Temerkhanov /* SMP Spin Table Definitions */ 63*746f985aSSergey Temerkhanov #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 64*746f985aSSergey Temerkhanov 65*746f985aSSergey Temerkhanov 66*746f985aSSergey Temerkhanov /* Generic Timer Definitions */ 67*746f985aSSergey Temerkhanov #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 68*746f985aSSergey Temerkhanov 69*746f985aSSergey Temerkhanov 70*746f985aSSergey Temerkhanov #define CONFIG_SYS_MEMTEST_START MEM_BASE 71*746f985aSSergey Temerkhanov #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 72*746f985aSSergey Temerkhanov 73*746f985aSSergey Temerkhanov /* Size of malloc() pool */ 74*746f985aSSergey Temerkhanov #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 75*746f985aSSergey Temerkhanov 76*746f985aSSergey Temerkhanov /* PL011 Serial Configuration */ 77*746f985aSSergey Temerkhanov 78*746f985aSSergey Temerkhanov #define CONFIG_PL01X_SERIAL 79*746f985aSSergey Temerkhanov #define CONFIG_PL011_CLOCK 24000000 80*746f985aSSergey Temerkhanov #define CONFIG_CONS_INDEX 1 81*746f985aSSergey Temerkhanov 82*746f985aSSergey Temerkhanov /* Generic Interrupt Controller Definitions */ 83*746f985aSSergey Temerkhanov #define GICD_BASE (0x801000000000) 84*746f985aSSergey Temerkhanov #define GICR_BASE (0x801000002000) 85*746f985aSSergey Temerkhanov #define CONFIG_SYS_SERIAL0 0x87e024000000 86*746f985aSSergey Temerkhanov #define CONFIG_SYS_SERIAL1 0x87e025000000 87*746f985aSSergey Temerkhanov 88*746f985aSSergey Temerkhanov #define CONFIG_BAUDRATE 115200 89*746f985aSSergey Temerkhanov 90*746f985aSSergey Temerkhanov /* Command line configuration */ 91*746f985aSSergey Temerkhanov #define CONFIG_MENU 92*746f985aSSergey Temerkhanov 93*746f985aSSergey Temerkhanov /* BOOTP options */ 94*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_BOOTFILESIZE 95*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_BOOTPATH 96*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_GATEWAY 97*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_HOSTNAME 98*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_PXE 99*746f985aSSergey Temerkhanov #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 100*746f985aSSergey Temerkhanov 101*746f985aSSergey Temerkhanov /* Miscellaneous configurable options */ 102*746f985aSSergey Temerkhanov #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 103*746f985aSSergey Temerkhanov 104*746f985aSSergey Temerkhanov /* Physical Memory Map */ 105*746f985aSSergey Temerkhanov #define CONFIG_NR_DRAM_BANKS 1 106*746f985aSSergey Temerkhanov #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 107*746f985aSSergey Temerkhanov #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 108*746f985aSSergey Temerkhanov #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 109*746f985aSSergey Temerkhanov 110*746f985aSSergey Temerkhanov /* Initial environment variables */ 111*746f985aSSergey Temerkhanov #define UBOOT_IMG_HEAD_SIZE 0x40 112*746f985aSSergey Temerkhanov /* C80000 - 0x40 */ 113*746f985aSSergey Temerkhanov #define CONFIG_EXTRA_ENV_SETTINGS \ 114*746f985aSSergey Temerkhanov "kernel_addr=08007ffc0\0" \ 115*746f985aSSergey Temerkhanov "fdt_addr=0x94C00000\0" \ 116*746f985aSSergey Temerkhanov "fdt_high=0x9fffffff\0" 117*746f985aSSergey Temerkhanov 118*746f985aSSergey Temerkhanov #define CONFIG_BOOTARGS \ 119*746f985aSSergey Temerkhanov "console=ttyAMA0,115200n8 " \ 120*746f985aSSergey Temerkhanov "earlycon=pl011,0x87e024000000 " \ 121*746f985aSSergey Temerkhanov "debug maxcpus=48 rootwait rw "\ 122*746f985aSSergey Temerkhanov "root=/dev/sda2 coherent_pool=16M" 123*746f985aSSergey Temerkhanov #define CONFIG_BOOTDELAY 5 124*746f985aSSergey Temerkhanov 125*746f985aSSergey Temerkhanov /* Do not preserve environment */ 126*746f985aSSergey Temerkhanov #define CONFIG_ENV_IS_NOWHERE 1 127*746f985aSSergey Temerkhanov #define CONFIG_ENV_SIZE 0x1000 128*746f985aSSergey Temerkhanov 129*746f985aSSergey Temerkhanov /* Monitor Command Prompt */ 130*746f985aSSergey Temerkhanov #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 131*746f985aSSergey Temerkhanov #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 132*746f985aSSergey Temerkhanov sizeof(CONFIG_SYS_PROMPT) + 16) 133*746f985aSSergey Temerkhanov #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 134*746f985aSSergey Temerkhanov #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 135*746f985aSSergey Temerkhanov #define CONFIG_SYS_LONGHELP 136*746f985aSSergey Temerkhanov #define CONFIG_CMDLINE_EDITING 1 137*746f985aSSergey Temerkhanov #define CONFIG_SYS_MAXARGS 64 /* max command args */ 138*746f985aSSergey Temerkhanov #define CONFIG_NO_RELOCATION 1 139*746f985aSSergey Temerkhanov #define CONFIG_LIB_RAND 140*746f985aSSergey Temerkhanov #define PLL_REF_CLK 50000000 /* 50 MHz */ 141*746f985aSSergey Temerkhanov #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 142*746f985aSSergey Temerkhanov 143*746f985aSSergey Temerkhanov #endif /* __THUNDERX_88XX_H__ */ 144