1 /*
2  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _CONFIG_THEADORABLE_H
8 #define _CONFIG_THEADORABLE_H
9 
10 /*
11  * High Level Configuration Options (easy to change)
12  */
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
14 
15 /*
16  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17  * for DDR ECC byte filling in the SPL before loading the main
18  * U-Boot into it.
19  */
20 #define	CONFIG_SYS_TEXT_BASE	0x00800000
21 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
22 
23 /*
24  * Commands configuration
25  */
26 #define CONFIG_CMD_ENV
27 #define CONFIG_CMD_SATA
28 
29 /*
30  * The debugging version enables USB support via defconfig.
31  * This version should also enable all other non-production
32  * interfaces / features.
33  */
34 #ifdef CONFIG_USB
35 #define CONFIG_CMD_PCI
36 #endif
37 
38 /* I2C */
39 #define CONFIG_SYS_I2C
40 #define CONFIG_SYS_I2C_MVTWSI
41 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
42 #define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
43 #define CONFIG_SYS_I2C_SLAVE		0x0
44 #define CONFIG_SYS_I2C_SPEED		100000
45 
46 /* USB/EHCI configuration */
47 #define CONFIG_EHCI_IS_TDI
48 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
49 
50 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
51 
52 /* SPI NOR flash default params, used by sf commands */
53 #define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
54 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
55 
56 /* Environment in SPI NOR flash */
57 #define CONFIG_ENV_IS_IN_SPI_FLASH
58 #define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
59 #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
60 #define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
61 #define CONFIG_ENV_OVERWRITE
62 
63 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
64 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
65 
66 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
67 #define CONFIG_SYS_ALT_MEMTEST
68 #define CONFIG_PREBOOT
69 
70 /* Keep device tree and initrd in lower memory so the kernel can access them */
71 #define CONFIG_EXTRA_ENV_SETTINGS	\
72 	"fdt_high=0x10000000\0"		\
73 	"initrd_high=0x10000000\0"
74 
75 /* SATA support */
76 #define CONFIG_SYS_SATA_MAX_DEVICE	1
77 #define CONFIG_SATA_MV
78 #define CONFIG_LIBATA
79 #define CONFIG_LBA48
80 #define CONFIG_EFI_PARTITION
81 #define CONFIG_DOS_PARTITION
82 
83 /* Additional FS support/configuration */
84 #define CONFIG_SUPPORT_VFAT
85 
86 /* PCIe support */
87 #ifdef CONFIG_CMD_PCI
88 #ifndef CONFIG_SPL_BUILD
89 #define CONFIG_PCI
90 #define CONFIG_PCI_MVEBU
91 #define CONFIG_PCI_PNP
92 #define CONFIG_BOARD_LATE_INIT		/* for PEX switch test */
93 #endif
94 #endif
95 
96 /* Enable LCD and reserve 512KB from top of memory*/
97 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
98 
99 #define CONFIG_VIDEO
100 #define CONFIG_CFB_CONSOLE
101 #define CONFIG_VGA_AS_SINGLE_DEVICE
102 #define CONFIG_CMD_BMP
103 
104 /* FPGA programming support */
105 #define CONFIG_FPGA
106 #define CONFIG_FPGA_ALTERA
107 #define CONFIG_FPGA_STRATIX_V
108 
109 /*
110  * Bootcounter
111  */
112 #define CONFIG_BOOTCOUNT_LIMIT
113 #define CONFIG_BOOTCOUNT_RAM
114 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
115 #define BOOTCOUNT_ADDR			0x1000
116 
117 /*
118  * mv-common.h should be defined after CMD configs since it used them
119  * to enable certain macros
120  */
121 #include "mv-common.h"
122 
123 /*
124  * Memory layout while starting into the bin_hdr via the
125  * BootROM:
126  *
127  * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
128  * 0x4000.4030			bin_hdr start address
129  * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
130  * 0x4007.fffc			BootROM stack top
131  *
132  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
133  * L2 cache thus cannot be used.
134  */
135 
136 /* SPL */
137 /* Defines for SPL */
138 #define CONFIG_SPL_FRAMEWORK
139 #define CONFIG_SPL_TEXT_BASE		0x40004030
140 #define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
141 
142 #define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
143 #define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
144 
145 #ifdef CONFIG_SPL_BUILD
146 #define CONFIG_SYS_MALLOC_SIMPLE
147 #endif
148 
149 #define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
150 #define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
151 
152 /* SPL related SPI defines */
153 #define CONFIG_SPL_SPI_LOAD
154 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
155 #define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
156 
157 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
158 #define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */
159 
160 #endif /* _CONFIG_THEADORABLE_H */
161