1 /* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_THEADORABLE_H 8 #define _CONFIG_THEADORABLE_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TEXT_BASE 0x00800000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 27 /* 28 * The debugging version enables USB support via defconfig. 29 * This version should also enable all other non-production 30 * interfaces / features. 31 */ 32 #ifdef CONFIG_USB 33 #define CONFIG_CMD_PCI 34 #endif 35 36 /* I2C */ 37 #define CONFIG_SYS_I2C 38 #define CONFIG_SYS_I2C_MVTWSI 39 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 40 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 41 #define CONFIG_SYS_I2C_SLAVE 0x0 42 #define CONFIG_SYS_I2C_SPEED 100000 43 44 /* USB/EHCI configuration */ 45 #define CONFIG_EHCI_IS_TDI 46 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 47 48 /* SPI NOR flash default params, used by sf commands */ 49 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 50 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 51 52 /* Environment in SPI NOR flash */ 53 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 54 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 55 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 59 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 60 61 #define CONFIG_SYS_ALT_MEMTEST 62 #define CONFIG_PREBOOT 63 64 /* Keep device tree and initrd in lower memory so the kernel can access them */ 65 #define CONFIG_EXTRA_ENV_SETTINGS \ 66 "fdt_high=0x10000000\0" \ 67 "initrd_high=0x10000000\0" 68 69 /* SATA support */ 70 #define CONFIG_SYS_SATA_MAX_DEVICE 1 71 #define CONFIG_SATA_MV 72 #define CONFIG_LIBATA 73 #define CONFIG_LBA48 74 75 /* Additional FS support/configuration */ 76 #define CONFIG_SUPPORT_VFAT 77 78 /* PCIe support */ 79 #ifdef CONFIG_CMD_PCI 80 #ifndef CONFIG_SPL_BUILD 81 #define CONFIG_PCI_MVEBU 82 #endif 83 #endif 84 85 /* Enable LCD and reserve 512KB from top of memory*/ 86 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 87 88 /* FPGA programming support */ 89 #define CONFIG_FPGA_STRATIX_V 90 91 /* 92 * Bootcounter 93 */ 94 #define CONFIG_BOOTCOUNT_LIMIT 95 #define CONFIG_BOOTCOUNT_RAM 96 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 97 #define BOOTCOUNT_ADDR 0x1000 98 99 /* 100 * mv-common.h should be defined after CMD configs since it used them 101 * to enable certain macros 102 */ 103 #include "mv-common.h" 104 105 /* 106 * Memory layout while starting into the bin_hdr via the 107 * BootROM: 108 * 109 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 110 * 0x4000.4030 bin_hdr start address 111 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 112 * 0x4007.fffc BootROM stack top 113 * 114 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 115 * L2 cache thus cannot be used. 116 */ 117 118 /* SPL */ 119 /* Defines for SPL */ 120 #define CONFIG_SPL_FRAMEWORK 121 #define CONFIG_SPL_TEXT_BASE 0x40004030 122 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 123 124 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 125 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 126 127 #ifdef CONFIG_SPL_BUILD 128 #define CONFIG_SYS_MALLOC_SIMPLE 129 #endif 130 131 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 132 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 133 134 /* SPL related SPI defines */ 135 #define CONFIG_SPL_SPI_LOAD 136 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 137 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 138 139 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 140 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 141 142 #endif /* _CONFIG_THEADORABLE_H */ 143