1 /*
2  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _CONFIG_THEADORABLE_H
8 #define _CONFIG_THEADORABLE_H
9 
10 /*
11  * High Level Configuration Options (easy to change)
12  */
13 
14 /*
15  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
16  * for DDR ECC byte filling in the SPL before loading the main
17  * U-Boot into it.
18  */
19 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
20 
21 /*
22  * Commands configuration
23  */
24 
25 /*
26  * The debugging version enables USB support via defconfig.
27  * This version should also enable all other non-production
28  * interfaces / features.
29  */
30 
31 /* I2C */
32 #define CONFIG_SYS_I2C
33 #define CONFIG_SYS_I2C_MVTWSI
34 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
35 #define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
36 #define CONFIG_SYS_I2C_SLAVE		0x0
37 #define CONFIG_SYS_I2C_SPEED		100000
38 
39 /* USB/EHCI configuration */
40 #define CONFIG_EHCI_IS_TDI
41 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
42 
43 /* SPI NOR flash default params, used by sf commands */
44 #define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
45 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
46 
47 /* Environment in SPI NOR flash */
48 #define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
49 #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
50 #define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
51 #define CONFIG_ENV_OVERWRITE
52 
53 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
54 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
55 
56 #define CONFIG_PREBOOT
57 
58 /* Keep device tree and initrd in lower memory so the kernel can access them */
59 #define CONFIG_EXTRA_ENV_SETTINGS	\
60 	"fdt_high=0x10000000\0"		\
61 	"initrd_high=0x10000000\0"
62 
63 /* SATA support */
64 #define CONFIG_SYS_SATA_MAX_DEVICE	1
65 #define CONFIG_LBA48
66 
67 /* PCIe support */
68 #ifdef CONFIG_CMD_PCI
69 #ifndef CONFIG_SPL_BUILD
70 #define CONFIG_PCI_MVEBU
71 #endif
72 #endif
73 
74 /* Enable LCD and reserve 512KB from top of memory*/
75 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
76 
77 /* FPGA programming support */
78 #define CONFIG_FPGA_STRATIX_V
79 
80 /*
81  * Bootcounter
82  */
83 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
84 #define BOOTCOUNT_ADDR			0x1000
85 
86 /*
87  * mv-common.h should be defined after CMD configs since it used them
88  * to enable certain macros
89  */
90 #include "mv-common.h"
91 
92 /*
93  * Memory layout while starting into the bin_hdr via the
94  * BootROM:
95  *
96  * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
97  * 0x4000.4030			bin_hdr start address
98  * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
99  * 0x4007.fffc			BootROM stack top
100  *
101  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
102  * L2 cache thus cannot be used.
103  */
104 
105 /* SPL */
106 /* Defines for SPL */
107 #define CONFIG_SPL_TEXT_BASE		0x40004030
108 #define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
109 
110 #define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
111 #define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
112 
113 #ifdef CONFIG_SPL_BUILD
114 #define CONFIG_SYS_MALLOC_SIMPLE
115 #endif
116 
117 #define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
118 #define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
119 
120 /* SPL related SPI defines */
121 #define CONFIG_SPL_SPI_LOAD
122 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
123 #define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
124 
125 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
126 #define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */
127 
128 #endif /* _CONFIG_THEADORABLE_H */
129