1 /* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_THEADORABLE_H 8 #define _CONFIG_THEADORABLE_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TEXT_BASE 0x00800000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 #define CONFIG_CMD_SATA 27 28 /* 29 * The debugging version enables USB support via defconfig. 30 * This version should also enable all other non-production 31 * interfaces / features. 32 */ 33 #ifdef CONFIG_USB 34 #define CONFIG_CMD_PCI 35 #endif 36 37 /* I2C */ 38 #define CONFIG_SYS_I2C 39 #define CONFIG_SYS_I2C_MVTWSI 40 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 41 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 42 #define CONFIG_SYS_I2C_SLAVE 0x0 43 #define CONFIG_SYS_I2C_SPEED 100000 44 45 /* USB/EHCI configuration */ 46 #define CONFIG_EHCI_IS_TDI 47 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 48 49 /* SPI NOR flash default params, used by sf commands */ 50 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 51 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 52 53 /* Environment in SPI NOR flash */ 54 #define CONFIG_ENV_IS_IN_SPI_FLASH 55 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 56 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 57 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 58 #define CONFIG_ENV_OVERWRITE 59 60 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 61 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 62 63 #define CONFIG_SYS_ALT_MEMTEST 64 #define CONFIG_PREBOOT 65 66 /* Keep device tree and initrd in lower memory so the kernel can access them */ 67 #define CONFIG_EXTRA_ENV_SETTINGS \ 68 "fdt_high=0x10000000\0" \ 69 "initrd_high=0x10000000\0" 70 71 /* SATA support */ 72 #define CONFIG_SYS_SATA_MAX_DEVICE 1 73 #define CONFIG_SATA_MV 74 #define CONFIG_LIBATA 75 #define CONFIG_LBA48 76 77 /* Additional FS support/configuration */ 78 #define CONFIG_SUPPORT_VFAT 79 80 /* PCIe support */ 81 #ifdef CONFIG_CMD_PCI 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_PCI_MVEBU 84 #endif 85 #endif 86 87 /* Enable LCD and reserve 512KB from top of memory*/ 88 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 89 90 /* FPGA programming support */ 91 #define CONFIG_FPGA 92 #define CONFIG_FPGA_ALTERA 93 #define CONFIG_FPGA_STRATIX_V 94 95 /* 96 * Bootcounter 97 */ 98 #define CONFIG_BOOTCOUNT_LIMIT 99 #define CONFIG_BOOTCOUNT_RAM 100 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 101 #define BOOTCOUNT_ADDR 0x1000 102 103 /* 104 * mv-common.h should be defined after CMD configs since it used them 105 * to enable certain macros 106 */ 107 #include "mv-common.h" 108 109 /* 110 * Memory layout while starting into the bin_hdr via the 111 * BootROM: 112 * 113 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 114 * 0x4000.4030 bin_hdr start address 115 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 116 * 0x4007.fffc BootROM stack top 117 * 118 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 119 * L2 cache thus cannot be used. 120 */ 121 122 /* SPL */ 123 /* Defines for SPL */ 124 #define CONFIG_SPL_FRAMEWORK 125 #define CONFIG_SPL_TEXT_BASE 0x40004030 126 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 127 128 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 129 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 130 131 #ifdef CONFIG_SPL_BUILD 132 #define CONFIG_SYS_MALLOC_SIMPLE 133 #endif 134 135 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 136 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 137 138 /* SPL related SPI defines */ 139 #define CONFIG_SPL_SPI_LOAD 140 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 141 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 142 143 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 144 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 145 146 #endif /* _CONFIG_THEADORABLE_H */ 147