1 /* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_THEADORABLE_H 8 #define _CONFIG_THEADORABLE_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 21 22 /* 23 * Commands configuration 24 */ 25 26 /* 27 * The debugging version enables USB support via defconfig. 28 * This version should also enable all other non-production 29 * interfaces / features. 30 */ 31 32 /* I2C */ 33 #define CONFIG_SYS_I2C 34 #define CONFIG_SYS_I2C_MVTWSI 35 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 36 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 37 #define CONFIG_SYS_I2C_SLAVE 0x0 38 #define CONFIG_SYS_I2C_SPEED 100000 39 40 /* USB/EHCI configuration */ 41 #define CONFIG_EHCI_IS_TDI 42 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 43 44 /* SPI NOR flash default params, used by sf commands */ 45 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 46 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 47 48 /* Environment in SPI NOR flash */ 49 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 50 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 51 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 55 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 56 57 #define CONFIG_SYS_ALT_MEMTEST 58 #define CONFIG_PREBOOT 59 60 /* Keep device tree and initrd in lower memory so the kernel can access them */ 61 #define CONFIG_EXTRA_ENV_SETTINGS \ 62 "fdt_high=0x10000000\0" \ 63 "initrd_high=0x10000000\0" 64 65 /* SATA support */ 66 #define CONFIG_SYS_SATA_MAX_DEVICE 1 67 #define CONFIG_LBA48 68 69 /* PCIe support */ 70 #ifdef CONFIG_CMD_PCI 71 #ifndef CONFIG_SPL_BUILD 72 #define CONFIG_PCI_MVEBU 73 #endif 74 #endif 75 76 /* Enable LCD and reserve 512KB from top of memory*/ 77 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 78 79 /* FPGA programming support */ 80 #define CONFIG_FPGA_STRATIX_V 81 82 /* 83 * Bootcounter 84 */ 85 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 86 #define BOOTCOUNT_ADDR 0x1000 87 88 /* 89 * mv-common.h should be defined after CMD configs since it used them 90 * to enable certain macros 91 */ 92 #include "mv-common.h" 93 94 /* 95 * Memory layout while starting into the bin_hdr via the 96 * BootROM: 97 * 98 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 99 * 0x4000.4030 bin_hdr start address 100 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 101 * 0x4007.fffc BootROM stack top 102 * 103 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 104 * L2 cache thus cannot be used. 105 */ 106 107 /* SPL */ 108 /* Defines for SPL */ 109 #define CONFIG_SPL_TEXT_BASE 0x40004030 110 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 111 112 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 113 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 114 115 #ifdef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MALLOC_SIMPLE 117 #endif 118 119 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 120 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 121 122 /* SPL related SPI defines */ 123 #define CONFIG_SPL_SPI_LOAD 124 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 125 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 126 127 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 128 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 129 130 #endif /* _CONFIG_THEADORABLE_H */ 131