1 /* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_THEADORABLE_H 8 #define _CONFIG_THEADORABLE_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TEXT_BASE 0x00800000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 27 /* 28 * The debugging version enables USB support via defconfig. 29 * This version should also enable all other non-production 30 * interfaces / features. 31 */ 32 33 /* I2C */ 34 #define CONFIG_SYS_I2C 35 #define CONFIG_SYS_I2C_MVTWSI 36 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 37 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 38 #define CONFIG_SYS_I2C_SLAVE 0x0 39 #define CONFIG_SYS_I2C_SPEED 100000 40 41 /* USB/EHCI configuration */ 42 #define CONFIG_EHCI_IS_TDI 43 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 44 45 /* SPI NOR flash default params, used by sf commands */ 46 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 47 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 48 49 /* Environment in SPI NOR flash */ 50 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 51 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 52 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 53 #define CONFIG_ENV_OVERWRITE 54 55 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 56 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 57 58 #define CONFIG_SYS_ALT_MEMTEST 59 #define CONFIG_PREBOOT 60 61 /* Keep device tree and initrd in lower memory so the kernel can access them */ 62 #define CONFIG_EXTRA_ENV_SETTINGS \ 63 "fdt_high=0x10000000\0" \ 64 "initrd_high=0x10000000\0" 65 66 /* SATA support */ 67 #define CONFIG_SYS_SATA_MAX_DEVICE 1 68 #define CONFIG_SATA_MV 69 #define CONFIG_LIBATA 70 #define CONFIG_LBA48 71 72 /* Additional FS support/configuration */ 73 #define CONFIG_SUPPORT_VFAT 74 75 /* PCIe support */ 76 #ifdef CONFIG_CMD_PCI 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_PCI_MVEBU 79 #endif 80 #endif 81 82 /* Enable LCD and reserve 512KB from top of memory*/ 83 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 84 85 /* FPGA programming support */ 86 #define CONFIG_FPGA_STRATIX_V 87 88 /* 89 * Bootcounter 90 */ 91 #define CONFIG_BOOTCOUNT_LIMIT 92 #define CONFIG_BOOTCOUNT_RAM 93 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 94 #define BOOTCOUNT_ADDR 0x1000 95 96 /* 97 * mv-common.h should be defined after CMD configs since it used them 98 * to enable certain macros 99 */ 100 #include "mv-common.h" 101 102 /* 103 * Memory layout while starting into the bin_hdr via the 104 * BootROM: 105 * 106 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 107 * 0x4000.4030 bin_hdr start address 108 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 109 * 0x4007.fffc BootROM stack top 110 * 111 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 112 * L2 cache thus cannot be used. 113 */ 114 115 /* SPL */ 116 /* Defines for SPL */ 117 #define CONFIG_SPL_FRAMEWORK 118 #define CONFIG_SPL_TEXT_BASE 0x40004030 119 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 120 121 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 122 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 123 124 #ifdef CONFIG_SPL_BUILD 125 #define CONFIG_SYS_MALLOC_SIMPLE 126 #endif 127 128 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 129 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 130 131 /* SPL related SPI defines */ 132 #define CONFIG_SPL_SPI_LOAD 133 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 134 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 135 136 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 137 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 138 139 #endif /* _CONFIG_THEADORABLE_H */ 140