1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  (C) Copyright 2010-2012
4  *  NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _TEGRA30_COMMON_H_
8 #define _TEGRA30_COMMON_H_
9 #include "tegra-common.h"
10 
11 /*
12  * NS16550 Configuration
13  */
14 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
15 
16 /*
17  * Miscellaneous configurable options
18  */
19 #define CONFIG_STACKBASE	0x83800000	/* 56MB */
20 
21 /*
22  * Memory layout for where various images get loaded by boot scripts:
23  *
24  * scriptaddr can be pretty much anywhere that doesn't conflict with something
25  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
26  *
27  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
28  *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
29  *
30  * kernel_addr_r must be within the first 128M of RAM in order for the
31  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
32  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
33  *   should not overlap that area, or the kernel will have to copy itself
34  *   somewhere else before decompression. Similarly, the address of any other
35  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
36  *   this up to 32M allows for a sizable kernel to be decompressed below the
37  *   compressed load address.
38  *
39  * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
40  *   the compressed kernel to be up to 32M too.
41  *
42  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
43  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
44  */
45 #define CONFIG_LOADADDR 0x81000000
46 #define MEM_LAYOUT_ENV_SETTINGS \
47 	"scriptaddr=0x90000000\0" \
48 	"pxefile_addr_r=0x90100000\0" \
49 	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
50 	"fdt_addr_r=0x83000000\0" \
51 	"ramdisk_addr_r=0x83100000\0"
52 
53 /* Defines for SPL */
54 #define CONFIG_SPL_TEXT_BASE		0x80108000
55 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
56 #define CONFIG_SPL_STACK		0x800ffffc
57 
58 /* For USB EHCI controller */
59 #define CONFIG_EHCI_IS_TDI
60 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
61 
62 #endif /* _TEGRA30_COMMON_H_ */
63