1 /* 2 * (C) Copyright 2013-2015 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA210_COMMON_H_ 9 #define _TEGRA210_COMMON_H_ 10 11 #include "tegra-common.h" 12 13 /* Cortex-A57 uses a cache line size of 64 bytes */ 14 #define CONFIG_SYS_CACHELINE_SIZE 64 15 16 /* 17 * NS16550 Configuration 18 */ 19 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 20 21 /* 22 * Miscellaneous configurable options 23 */ 24 #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 25 26 /*----------------------------------------------------------------------- 27 * Physical Memory Map 28 */ 29 #define CONFIG_SYS_TEXT_BASE 0x8010E000 30 31 /* Generic Interrupt Controller */ 32 #define CONFIG_GICV2 33 34 /* 35 * Memory layout for where various images get loaded by boot scripts: 36 * 37 * scriptaddr can be pretty much anywhere that doesn't conflict with something 38 * else. Put it above BOOTMAPSZ to eliminate conflicts. 39 * 40 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 41 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 42 * 43 * kernel_addr_r must be within the first 128M of RAM in order for the 44 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 45 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 46 * should not overlap that area, or the kernel will have to copy itself 47 * somewhere else before decompression. Similarly, the address of any other 48 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 49 * this up to 16M allows for a sizable kernel to be decompressed below the 50 * compressed load address. 51 * 52 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 53 * the compressed kernel to be up to 16M too. 54 * 55 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 56 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 57 */ 58 #define CONFIG_LOADADDR 0x81000000 59 #define MEM_LAYOUT_ENV_SETTINGS \ 60 "scriptaddr=0x90000000\0" \ 61 "pxefile_addr_r=0x90100000\0" \ 62 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 63 "fdt_addr_r=0x82000000\0" \ 64 "ramdisk_addr_r=0x82100000\0" 65 66 /* Defines for SPL */ 67 #define CONFIG_SPL_TEXT_BASE 0x80108000 68 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 69 #define CONFIG_SPL_STACK 0x800ffffc 70 71 /* For USB EHCI controller */ 72 #define CONFIG_EHCI_IS_TDI 73 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 74 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 75 76 #endif /* _TEGRA210_COMMON_H_ */ 77