1 /* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __TEGRA20_COMMON_H 25 #define __TEGRA20_COMMON_H 26 #include <asm/sizes.h> 27 28 /* 29 * QUOTE(m) will evaluate to a string version of the value of the macro m 30 * passed in. The extra level of indirection here is to first evaluate the 31 * macro m before applying the quoting operator. 32 */ 33 #define QUOTE_(m) #m 34 #define QUOTE(m) QUOTE_(m) 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ 40 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ 41 #define CONFIG_TEGRA /* which is a Tegra generic machine */ 42 #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ 43 44 #define CONFIG_SYS_CACHELINE_SIZE 32 45 46 #define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ 47 48 #include <asm/arch/tegra20.h> /* get chip and board defs */ 49 50 /* 51 * Display CPU and Board information 52 */ 53 #define CONFIG_DISPLAY_CPUINFO 54 #define CONFIG_DISPLAY_BOARDINFO 55 56 #define CONFIG_SKIP_LOWLEVEL_INIT 57 58 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 59 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 60 61 #ifdef CONFIG_TEGRA20_LP0 62 #define TEGRA_LP0_ADDR 0x1C406000 63 #define TEGRA_LP0_SIZE 0x2000 64 #define TEGRA_LP0_VEC \ 65 "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " " 66 #else 67 #define TEGRA_LP0_VEC 68 #endif 69 70 /* Environment */ 71 #define CONFIG_ENV_VARS_UBOOT_CONFIG 72 #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ 73 74 /* 75 * Size of malloc() pool 76 */ 77 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ 78 79 /* 80 * PllX Configuration 81 */ 82 #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ 83 84 /* 85 * NS16550 Configuration 86 */ 87 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 88 89 #define CONFIG_SYS_NS16550 90 #define CONFIG_SYS_NS16550_SERIAL 91 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 92 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 93 94 /* 95 * select serial console configuration 96 */ 97 #define CONFIG_CONS_INDEX 1 98 99 /* allow to overwrite serial and ethaddr */ 100 #define CONFIG_ENV_OVERWRITE 101 #define CONFIG_BAUDRATE 115200 102 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 103 115200} 104 105 /* 106 * This parameter affects a TXFILLTUNING field that controls how much data is 107 * sent to the latency fifo before it is sent to the wire. Without this 108 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 109 * packets depending on the buffer address and size. 110 */ 111 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 112 #define CONFIG_EHCI_IS_TDI 113 #define CONFIG_EHCI_DCACHE 114 115 /* Total I2C ports on Tegra20 */ 116 #define TEGRA_I2C_NUM_CONTROLLERS 4 117 118 /* include default commands */ 119 #include <config_cmd_default.h> 120 121 /* remove unused commands */ 122 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 123 #undef CONFIG_CMD_FPGA /* FPGA configuration support */ 124 #undef CONFIG_CMD_IMI 125 #undef CONFIG_CMD_IMLS 126 #undef CONFIG_CMD_NFS /* NFS support */ 127 #undef CONFIG_CMD_NET /* network support */ 128 129 /* turn on command-line edit/hist/auto */ 130 #define CONFIG_CMDLINE_EDITING 131 #define CONFIG_COMMAND_HISTORY 132 #define CONFIG_AUTO_COMPLETE 133 134 #define CONFIG_SYS_NO_FLASH 135 136 /* Environment information, boards can override if required */ 137 #define CONFIG_CONSOLE_MUX 138 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 139 #define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \ 140 "stdout=serial\0" \ 141 "stderr=serial\0" 142 143 #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ 144 #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ 145 146 /* 147 * Miscellaneous configurable options 148 */ 149 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 150 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 151 #define CONFIG_SYS_PROMPT V_PROMPT 152 /* 153 * Increasing the size of the IO buffer as default nfsargs size is more 154 * than 256 and so it is not possible to edit it 155 */ 156 #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ 157 /* Print Buffer Size */ 158 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 159 sizeof(CONFIG_SYS_PROMPT) + 16) 160 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 161 /* Boot Argument Buffer Size */ 162 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 163 164 #define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000) 165 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 166 167 #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ 168 #define CONFIG_SYS_HZ 1000 169 170 /*----------------------------------------------------------------------- 171 * Stack sizes 172 * 173 * The stack sizes are set up in start.S using the settings below 174 */ 175 #define CONFIG_STACKBASE 0x2800000 /* 40MB */ 176 #define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/ 177 178 /*----------------------------------------------------------------------- 179 * Physical Memory Map 180 */ 181 #define CONFIG_NR_DRAM_BANKS 1 182 #define PHYS_SDRAM_1 TEGRA20_SDRC_CS0 183 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ 184 185 #define CONFIG_SYS_TEXT_BASE 0x00108000 186 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 187 188 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE 189 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN 190 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 191 CONFIG_SYS_INIT_RAM_SIZE - \ 192 GENERATED_GBL_DATA_SIZE) 193 194 #define CONFIG_TEGRA_GPIO 195 #define CONFIG_CMD_GPIO 196 #define CONFIG_CMD_ENTERRCM 197 #define CONFIG_CMD_BOOTZ 198 #endif /* __TEGRA20_COMMON_H */ 199