1 /* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA20_COMMON_H_ 9 #define _TEGRA20_COMMON_H_ 10 #include "tegra-common.h" 11 12 /* Cortex-A9 uses a cache line size of 32 bytes */ 13 #define CONFIG_SYS_CACHELINE_SIZE 32 14 15 /* 16 * Errata configuration 17 */ 18 #define CONFIG_ARM_ERRATA_716044 19 #define CONFIG_ARM_ERRATA_742230 20 #define CONFIG_ARM_ERRATA_751472 21 22 /* 23 * NS16550 Configuration 24 */ 25 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 26 27 /* Environment information, boards can override if required */ 28 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ 29 30 /* 31 * Miscellaneous configurable options 32 */ 33 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ 34 #define CONFIG_STACKBASE 0x02800000 /* 40MB */ 35 36 /*----------------------------------------------------------------------- 37 * Physical Memory Map 38 */ 39 #define CONFIG_SYS_TEXT_BASE 0x0010E000 40 41 /* 42 * Memory layout for where various images get loaded by boot scripts: 43 * 44 * scriptaddr can be pretty much anywhere that doesn't conflict with something 45 * else. Put it above BOOTMAPSZ to eliminate conflicts. 46 * 47 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 48 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 49 * 50 * kernel_addr_r must be within the first 128M of RAM in order for the 51 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 52 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 53 * should not overlap that area, or the kernel will have to copy itself 54 * somewhere else before decompression. Similarly, the address of any other 55 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 56 * this up to 16M allows for a sizable kernel to be decompressed below the 57 * compressed load address. 58 * 59 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 60 * the compressed kernel to be up to 16M too. 61 * 62 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 63 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 64 */ 65 #define MEM_LAYOUT_ENV_SETTINGS \ 66 "scriptaddr=0x10000000\0" \ 67 "pxefile_addr_r=0x10100000\0" \ 68 "kernel_addr_r=0x01000000\0" \ 69 "fdt_addr_r=0x02000000\0" \ 70 "ramdisk_addr_r=0x02100000\0" 71 72 /* Defines for SPL */ 73 #define CONFIG_SPL_TEXT_BASE 0x00108000 74 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 75 #define CONFIG_SPL_STACK 0x000ffffc 76 77 /* Align LCD to 1MB boundary */ 78 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 79 80 #ifdef CONFIG_TEGRA_LP0 81 #define TEGRA_LP0_ADDR 0x1C406000 82 #define TEGRA_LP0_SIZE 0x2000 83 #define TEGRA_LP0_VEC \ 84 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 85 "@" __stringify(TEGRA_LP0_ADDR) " " 86 #else 87 #define TEGRA_LP0_VEC 88 #endif 89 90 /* 91 * This parameter affects a TXFILLTUNING field that controls how much data is 92 * sent to the latency fifo before it is sent to the wire. Without this 93 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 94 * packets depending on the buffer address and size. 95 */ 96 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 97 #define CONFIG_EHCI_IS_TDI 98 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 99 100 /* Total I2C ports on Tegra20 */ 101 #define TEGRA_I2C_NUM_CONTROLLERS 4 102 103 #define CONFIG_SYS_NAND_SELF_INIT 104 #define CONFIG_SYS_NAND_ONFI_DETECTION 105 106 #endif /* _TEGRA20_COMMON_H_ */ 107